diff options
| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2023-03-02 13:37:02 +0000 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2023-03-07 12:39:00 -0500 |
| commit | 010746ae1db7f52700cb2e2c46eb94f299cfa0d2 (patch) | |
| tree | a5dbd0d96b10f1a66e5a251f676cd7407d1e9099 /hw/pci | |
| parent | f18e29fc90cf271bae0c671151d0f55bd7649d52 (diff) | |
| download | qemu-010746ae1db7f52700cb2e2c46eb94f299cfa0d2.zip qemu-010746ae1db7f52700cb2e2c46eb94f299cfa0d2.tar.gz qemu-010746ae1db7f52700cb2e2c46eb94f299cfa0d2.tar.bz2 | |
hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20230302133709.30373-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Diffstat (limited to 'hw/pci')
| -rw-r--r-- | hw/pci/pcie_aer.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c index 9a19be4..909e027 100644 --- a/hw/pci/pcie_aer.c +++ b/hw/pci/pcie_aer.c @@ -112,6 +112,10 @@ int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset, pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS, PCI_ERR_UNC_SUPPORTED); + pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK, + PCI_ERR_UNC_MASK_DEFAULT); + pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK, + PCI_ERR_UNC_SUPPORTED); pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER, PCI_ERR_UNC_SEVERITY_DEFAULT); |