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| author | Mao Zhongyi <maozy.fnst@cn.fujitsu.com> | 2017-06-27 14:16:52 +0800 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2017-07-03 22:29:49 +0300 |
| commit | f8cd1b0201c41d88bb97dcafb80348a0e88d8805 (patch) | |
| tree | 870bf5bd0c61a8193a878dfbe508b14ca59a5c1b /hw/pci | |
| parent | 27841278574a8687d3852dc51b0eeade218339cc (diff) | |
| download | qemu-f8cd1b0201c41d88bb97dcafb80348a0e88d8805.zip qemu-f8cd1b0201c41d88bb97dcafb80348a0e88d8805.tar.gz qemu-f8cd1b0201c41d88bb97dcafb80348a0e88d8805.tar.bz2 | |
pci: Convert to realize
Convert i82801b11, io3130_upstream, io3130_downstream and
pcie_root_port devices to realize.
Cc: mst@redhat.com
Cc: marcel@redhat.com
Cc: armbru@redhat.com
Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/pci')
| -rw-r--r-- | hw/pci/pci_bridge.c | 7 | ||||
| -rw-r--r-- | hw/pci/pcie.c | 24 |
2 files changed, 20 insertions, 11 deletions
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index bb0f3a3..720119b 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -41,15 +41,14 @@ #define PCI_SSVID_SSID 6 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, - uint16_t svid, uint16_t ssid) + uint16_t svid, uint16_t ssid, + Error **errp) { int pos; - Error *local_err = NULL; pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, - PCI_SSVID_SIZEOF, &local_err); + PCI_SSVID_SIZEOF, errp); if (pos < 0) { - error_report_err(local_err); return pos; } diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index f187512..32191f2 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -86,19 +86,19 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version) pci_set_word(cmask + PCI_EXP_LNKSTA, 0); } -int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port) +int pcie_cap_init(PCIDevice *dev, uint8_t offset, + uint8_t type, uint8_t port, + Error **errp) { /* PCIe cap v2 init */ int pos; uint8_t *exp_cap; - Error *local_err = NULL; assert(pci_is_express(dev)); pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset, - PCI_EXP_VER2_SIZEOF, &local_err); + PCI_EXP_VER2_SIZEOF, errp); if (pos < 0) { - error_report_err(local_err); return pos; } dev->exp.exp_cap = pos; @@ -147,6 +147,8 @@ static int pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) { uint8_t type = PCI_EXP_TYPE_ENDPOINT; + Error *local_err = NULL; + int ret; /* * Windows guests will report Code 10, device cannot start, if @@ -157,9 +159,17 @@ pcie_endpoint_cap_common_init(PCIDevice *dev, uint8_t offset, uint8_t cap_size) type = PCI_EXP_TYPE_RC_END; } - return (cap_size == PCI_EXP_VER1_SIZEOF) - ? pcie_cap_v1_init(dev, offset, type, 0) - : pcie_cap_init(dev, offset, type, 0); + if (cap_size == PCI_EXP_VER1_SIZEOF) { + return pcie_cap_v1_init(dev, offset, type, 0); + } else { + ret = pcie_cap_init(dev, offset, type, 0, &local_err); + + if (ret < 0) { + error_report_err(local_err); + } + + return ret; + } } int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset) |