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| author | Marcel Apfelbaum <marcel.a@redhat.com> | 2014-06-23 17:32:48 +0300 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2014-06-23 17:48:42 +0300 |
| commit | f23b6bdc3c30c77ba0dffaa6de5e398dc3c49c51 (patch) | |
| tree | d60338e3cc88b6d1cee7a8a6778a9757657dfd6a /hw/pci/pcie.c | |
| parent | e4bcd27c86d20d6f1bc06a34e6612c18534a4968 (diff) | |
| download | qemu-f23b6bdc3c30c77ba0dffaa6de5e398dc3c49c51.zip qemu-f23b6bdc3c30c77ba0dffaa6de5e398dc3c49c51.tar.gz qemu-f23b6bdc3c30c77ba0dffaa6de5e398dc3c49c51.tar.bz2 | |
hw/pcie: implement power controller functionality
It is needed by hot-unplug in order to get an indication
from the OS when the device can be physically detached.
Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/pci/pcie.c')
| -rw-r--r-- | hw/pci/pcie.c | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index ae92f00..d6d9eb8 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -294,6 +294,15 @@ void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_ABP); + if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { + pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP, + PCI_EXP_SLTCAP_PCP); + pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, + PCI_EXP_SLTCTL_PCC); + pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL, + PCI_EXP_SLTCTL_PCC); + } + pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL, PCI_EXP_SLTCTL_PIC | PCI_EXP_SLTCTL_AIC); @@ -327,6 +336,10 @@ void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot) void pcie_cap_slot_reset(PCIDevice *dev) { uint8_t *exp_cap = dev->config + dev->exp.exp_cap; + uint8_t port_type = pcie_cap_get_type(dev); + + assert(port_type == PCI_EXP_TYPE_DOWNSTREAM || + port_type == PCI_EXP_TYPE_ROOT_PORT); PCIE_DEV_PRINTF(dev, "reset\n"); @@ -339,9 +352,27 @@ void pcie_cap_slot_reset(PCIDevice *dev) PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE); pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, - PCI_EXP_SLTCTL_PIC_OFF | PCI_EXP_SLTCTL_AIC_OFF); + if (dev->cap_present & QEMU_PCIE_SLTCAP_PCP) { + bool populated; + uint16_t pic; + + /* Downstream ports enforce device number 0. */ + populated = (pci_bridge_get_sec_bus(PCI_BRIDGE(dev))->devices[0] != NULL); + + if (populated) { + pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL, + PCI_EXP_SLTCTL_PCC); + } else { + pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, + PCI_EXP_SLTCTL_PCC); + } + + pic = populated ? PCI_EXP_SLTCTL_PIC_ON : PCI_EXP_SLTCTL_PIC_OFF; + pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL, pic); + } + pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_EIS |/* on reset, the lock is released */ |