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author | Huai-Cheng Kuo <hchkuo@avery-design.com.tw> | 2022-10-14 16:10:41 +0100 |
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committer | Michael S. Tsirkin <mst@redhat.com> | 2022-11-07 13:12:19 -0500 |
commit | 5fb52f6cc8f621f2e51d181d81401d14e4d45102 (patch) | |
tree | aab49203893ec2446f119caca96ac20e60ce560f /hw/pci/meson.build | |
parent | 535824f596d2e767a8824dde43ec11b6dfa9286a (diff) | |
download | qemu-5fb52f6cc8f621f2e51d181d81401d14e4d45102.zip qemu-5fb52f6cc8f621f2e51d181d81401d14e4d45102.tar.gz qemu-5fb52f6cc8f621f2e51d181d81401d14e4d45102.tar.bz2 |
hw/pci: PCIe Data Object Exchange emulation
Emulation of PCIe Data Object Exchange (DOE)
PCIE Base Specification r6.0 6.3 Data Object Exchange
Supports multiple DOE PCIe Extended Capabilities for a single PCIe
device. For each capability, a static array of DOEProtocol should be passed
to pcie_doe_init(). The protocols in that array will be registered under
the DOE capability structure. For each protocol, vendor ID, type, and
corresponding callback function (handle_request()) should be implemented.
This callback function represents how the DOE request for corresponding
protocol will be handled.
pcie_doe_{read/write}_config() must be appended to corresponding PCI
device's config_read/write() handler to enable DOE access. In
pcie_doe_read_config(), false will be returned if pci_config_read()
offset is not within DOE capability range. In pcie_doe_write_config(),
the function will have no affect if the address is not within the related
DOE PCIE extended capability.
Signed-off-by: Huai-Cheng Kuo <hchkuo@avery-design.com.tw>
Signed-off-by: Chris Browy <cbrowy@avery-design.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20221014151045.24781-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/pci/meson.build')
-rw-r--r-- | hw/pci/meson.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/pci/meson.build b/hw/pci/meson.build index bcc9c75..5aff7ed 100644 --- a/hw/pci/meson.build +++ b/hw/pci/meson.build @@ -13,6 +13,7 @@ pci_ss.add(files( # allow plugging PCIe devices into PCI buses, include them even if # CONFIG_PCI_EXPRESS=n. pci_ss.add(files('pcie.c', 'pcie_aer.c')) +pci_ss.add(files('pcie_doe.c')) softmmu_ss.add(when: 'CONFIG_PCI_EXPRESS', if_true: files('pcie_port.c', 'pcie_host.c')) softmmu_ss.add_all(when: 'CONFIG_PCI', if_true: pci_ss) |