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| author | Isaku Yamahata <yamahata@valinux.co.jp> | 2009-11-12 14:58:42 +0900 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2009-12-01 17:52:15 +0200 |
| commit | 2c56b44b88d913c4f7acb444071052b55b37da34 (patch) | |
| tree | 8340ee329001fc256bc57132f59bfecba5ea6c4a /hw/pci.h | |
| parent | fb47a2e983f3e0b4c9d36fe0d31ed8a1224e767b (diff) | |
| download | qemu-2c56b44b88d913c4f7acb444071052b55b37da34.zip qemu-2c56b44b88d913c4f7acb444071052b55b37da34.tar.gz qemu-2c56b44b88d913c4f7acb444071052b55b37da34.tar.bz2 | |
pci: remove unused constants
This patch removes unused constants committed by
fb23162885f7fd8cf7334bed22c25ac32c7d8b9d.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/pci.h')
| -rw-r--r-- | hw/pci.h | 9 |
1 files changed, 0 insertions, 9 deletions
@@ -101,14 +101,6 @@ typedef struct PCIIORegion { #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ #define PCI_COMMAND_MASTER 0x4 /* Enable bus master */ -#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ -#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ -#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ -#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ -#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ -#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ -#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ -#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ #define PCI_STATUS 0x06 /* 16 bits */ #define PCI_REVISION_ID 0x08 /* 8 bits */ #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ @@ -128,7 +120,6 @@ typedef struct PCIIORegion { #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ -#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ #define PCI_IO_LIMIT 0x1d #define PCI_IO_RANGE_TYPE_32 0x01 |