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| author | Michael Tokarev <mjt@tls.msk.ru> | 2023-07-14 14:27:04 +0300 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-09-20 07:54:34 +0300 |
| commit | f1c0cff8a28ac25f48ecaea672eb3d68250bb3c4 (patch) | |
| tree | db97cf9d628a18c15a28e0af6f92a818dbd80ef0 /hw/pci-host/gt64120.c | |
| parent | 2431f4f184339f679ff665c75e927fc24f7bd430 (diff) | |
| download | qemu-f1c0cff8a28ac25f48ecaea672eb3d68250bb3c4.zip qemu-f1c0cff8a28ac25f48ecaea672eb3d68250bb3c4.tar.gz qemu-f1c0cff8a28ac25f48ecaea672eb3d68250bb3c4.tar.bz2 | |
hw/pci: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/pci-host/gt64120.c')
| -rw-r--r-- | hw/pci-host/gt64120.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index 82c15ed..143bf05 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -331,9 +331,9 @@ static void gt64120_update_pci_cfgdata_mapping(GT64120State *s) /* * The setting of the MByteSwap bit and MWordSwap bit in the PCI Internal * Command Register determines how data transactions from the CPU to/from - * PCI are handled along with the setting of the Endianess bit in the CPU + * PCI are handled along with the setting of the Endianness bit in the CPU * Configuration Register. See: - * - Table 16: 32-bit PCI Transaction Endianess + * - Table 16: 32-bit PCI Transaction Endianness * - Table 158: PCI_0 Command, Offset: 0xc00 */ |