diff options
author | Andreas Färber <afaerber@suse.de> | 2012-03-14 01:38:23 +0100 |
---|---|---|
committer | Andreas Färber <afaerber@suse.de> | 2012-03-14 22:20:26 +0100 |
commit | 4a8fa5dca1780d7064abd9af578cba40cc0e666d (patch) | |
tree | 339584f6c17840091fe96f03def7f667860fb54d /hw/pc.c | |
parent | fc9bb1769706d4b3ac48e52d4639505bc1ce7392 (diff) | |
download | qemu-4a8fa5dca1780d7064abd9af578cba40cc0e666d.zip qemu-4a8fa5dca1780d7064abd9af578cba40cc0e666d.tar.gz qemu-4a8fa5dca1780d7064abd9af578cba40cc0e666d.tar.bz2 |
i386 hw/: Don't use CPUState
Scripted conversion:
for file in hw/apic.h hw/kvm/apic.c hw/kvmvapic.c hw/pc.c hw/vmport.c hw/xen_machine_pv.c; do
sed -i "s/CPUState/CPUX86State/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/pc.c')
-rw-r--r-- | hw/pc.c | 20 |
1 files changed, 10 insertions, 10 deletions
@@ -140,7 +140,7 @@ void cpu_smm_register(cpu_set_smm_t callback, void *arg) smm_arg = arg; } -void cpu_smm_update(CPUState *env) +void cpu_smm_update(CPUX86State *env) { if (smm_set && smm_arg && env == first_cpu) smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); @@ -148,7 +148,7 @@ void cpu_smm_update(CPUState *env) /* IRQ handling */ -int cpu_get_pic_interrupt(CPUState *env) +int cpu_get_pic_interrupt(CPUX86State *env) { int intno; @@ -167,7 +167,7 @@ int cpu_get_pic_interrupt(CPUState *env) static void pic_irq_request(void *opaque, int irq, int level) { - CPUState *env = first_cpu; + CPUX86State *env = first_cpu; DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); if (env->apic_state) { @@ -522,7 +522,7 @@ type_init(port92_register_types) static void handle_a20_line_change(void *opaque, int irq, int level) { - CPUState *cpu = opaque; + CPUX86State *cpu = opaque; /* XXX: send to all CPUs ? */ /* XXX: add logic to handle multiple A20 line sources */ @@ -869,7 +869,7 @@ void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) nb_ne2k++; } -int cpu_is_bsp(CPUState *env) +int cpu_is_bsp(CPUX86State *env) { /* We hard-wire the BSP to the first CPU. */ return env->cpu_index == 0; @@ -917,7 +917,7 @@ static DeviceState *apic_init(void *env, uint8_t apic_id) void pc_acpi_smi_interrupt(void *opaque, int irq, int level) { - CPUState *s = opaque; + CPUX86State *s = opaque; if (level) { cpu_interrupt(s, CPU_INTERRUPT_SMI); @@ -926,15 +926,15 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level) static void pc_cpu_reset(void *opaque) { - CPUState *env = opaque; + CPUX86State *env = opaque; cpu_state_reset(env); env->halted = !cpu_is_bsp(env); } -static CPUState *pc_new_cpu(const char *cpu_model) +static CPUX86State *pc_new_cpu(const char *cpu_model) { - CPUState *env; + CPUX86State *env; env = cpu_init(cpu_model); if (!env) { @@ -1070,7 +1070,7 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) static void cpu_request_exit(void *opaque, int irq, int level) { - CPUState *env = cpu_single_env; + CPUX86State *env = cpu_single_env; if (env && level) { cpu_exit(env); |