apic: qdev conversion cleanup

Make APICState completely private to apic.c by using DeviceState
in external APIs.

Move apic_init() to pc.c.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

1 files changed, 30 insertions, 1 deletions

diff --git a/hw/pc.c b/hw/pc.c
index bec1a88..1848151 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -35,6 +35,7 @@
 #include "elf.h"
 #include "multiboot.h"
 #include "mc146818rtc.h"
+#include "msix.h"
 #include "sysbus.h"
 #include "sysemu.h"
 
@@ -64,6 +65,8 @@
 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
 
+#define MSI_ADDR_BASE 0xfee00000
+
 #define E820_NR_ENTRIES		16
 
 struct e820_entry {
@@ -754,7 +757,7 @@ int cpu_is_bsp(CPUState *env)
     return env->cpu_index == 0;
 }
 
-APICState *cpu_get_current_apic(void)
+DeviceState *cpu_get_current_apic(void)
 {
     if (cpu_single_env) {
         return cpu_single_env->apic_state;
@@ -763,6 +766,32 @@ APICState *cpu_get_current_apic(void)
     }
 }
 
+static DeviceState *apic_init(void *env, uint8_t apic_id)
+{
+    DeviceState *dev;
+    SysBusDevice *d;
+    static int apic_mapped;
+
+    dev = qdev_create(NULL, "apic");
+    qdev_prop_set_uint8(dev, "id", apic_id);
+    qdev_prop_set_ptr(dev, "cpu_env", env);
+    qdev_init_nofail(dev);
+    d = sysbus_from_qdev(dev);
+
+    /* XXX: mapping more APICs at the same memory location */
+    if (apic_mapped == 0) {
+        /* NOTE: the APIC is directly connected to the CPU - it is not
+           on the global memory bus. */
+        /* XXX: what if the base changes? */
+        sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
+        apic_mapped = 1;
+    }
+
+    msix_supported = 1;
+
+    return dev;
+}
+
 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
    BIOS will read it and start S3 resume at POST Entry */
 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)