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author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-03 00:46:16 +0000 |
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committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-03 00:46:16 +0000 |
commit | 66450b1596fddd03204b54cc4f9fb99fb928c857 (patch) | |
tree | e7b735b38e888646367dddf717a157968cc7136e /hw/omap.h | |
parent | 7fc42b4bbddc47a6bebc281ee96e9ddcd537d46e (diff) | |
download | qemu-66450b1596fddd03204b54cc4f9fb99fb928c857.zip qemu-66450b1596fddd03204b54cc4f9fb99fb928c857.tar.gz qemu-66450b1596fddd03204b54cc4f9fb99fb928c857.tar.bz2 |
Implement OMAP PWL (backlight) module.
Fix GPIO clock name and output level change notifications.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3512 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/omap.h')
-rw-r--r-- | hw/omap.h | 11 |
1 files changed, 11 insertions, 0 deletions
@@ -534,6 +534,14 @@ struct omap_mpu_state_s { struct omap_uwire_s *microwire; + struct { + target_phys_addr_t base; + uint8_t output; + uint8_t level; + uint8_t enable; + int clk; + } pwl; + /* MPU private TIPB peripherals */ struct omap_intr_handler_s *ih[2]; @@ -615,6 +623,9 @@ void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, # define OMAP_RO_REG(paddr) \ printf("%s: Read-only register " OMAP_FMT_plx "\n", \ __FUNCTION__, paddr) +# define OMAP_8B_REG(paddr) \ + printf("%s: 8-bit register " OMAP_FMT_plx "\n", \ + __FUNCTION__, paddr) # define OMAP_16B_REG(paddr) \ printf("%s: 16-bit register " OMAP_FMT_plx "\n", \ __FUNCTION__, paddr) |