aboutsummaryrefslogtreecommitdiff
path: root/hw/nvme
diff options
context:
space:
mode:
authorKlaus Jensen <k.jensen@samsung.com>2022-11-09 11:40:16 +0100
committerKlaus Jensen <k.jensen@samsung.com>2023-01-11 08:41:19 +0100
commit973f76cf7743545a5d8a0a8bfdfe2cd02aa3e238 (patch)
tree1203268a21c14ac4b18012835a059506d587c5f1 /hw/nvme
parent784fd35387e9e6b42e3f365ddf44263eb25de8f7 (diff)
downloadqemu-973f76cf7743545a5d8a0a8bfdfe2cd02aa3e238.zip
qemu-973f76cf7743545a5d8a0a8bfdfe2cd02aa3e238.tar.gz
qemu-973f76cf7743545a5d8a0a8bfdfe2cd02aa3e238.tar.bz2
hw/nvme: cleanup error reporting in nvme_init_pci()
Replace the local Error variable with errp and ERRP_GUARD() and change the return value to bool. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Diffstat (limited to 'hw/nvme')
-rw-r--r--hw/nvme/ctrl.c25
1 files changed, 12 insertions, 13 deletions
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index b21455a..f25cc2c 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -7290,15 +7290,14 @@ static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset)
return 0;
}
-static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
+static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
{
+ ERRP_GUARD();
uint8_t *pci_conf = pci_dev->config;
uint64_t bar_size;
unsigned msix_table_offset, msix_pba_offset;
int ret;
- Error *err = NULL;
-
pci_conf[PCI_INTERRUPT_PIN] = 1;
pci_config_set_prog_interface(pci_conf, 0x2);
@@ -7335,14 +7334,14 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
}
ret = msix_init(pci_dev, n->params.msix_qsize,
&n->bar0, 0, msix_table_offset,
- &n->bar0, 0, msix_pba_offset, 0, &err);
- if (ret < 0) {
- if (ret == -ENOTSUP) {
- warn_report_err(err);
- } else {
- error_propagate(errp, err);
- return ret;
- }
+ &n->bar0, 0, msix_pba_offset, 0, errp);
+ if (ret == -ENOTSUP) {
+ /* report that msix is not supported, but do not error out */
+ warn_report_err(*errp);
+ *errp = NULL;
+ } else if (ret < 0) {
+ /* propagate error to caller */
+ return false;
}
nvme_update_msixcap_ts(pci_dev, n->conf_msix_qsize);
@@ -7359,7 +7358,7 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
nvme_init_sriov(n, pci_dev, 0x120);
}
- return 0;
+ return true;
}
static void nvme_init_subnqn(NvmeCtrl *n)
@@ -7535,7 +7534,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
return;
}
nvme_init_state(n);
- if (nvme_init_pci(n, pci_dev, errp)) {
+ if (!nvme_init_pci(n, pci_dev, errp)) {
return;
}
nvme_init_ctrl(n, pci_dev);