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| author | Klaus Jensen <k.jensen@samsung.com> | 2021-07-13 14:34:52 +0200 |
|---|---|---|
| committer | Klaus Jensen <k.jensen@samsung.com> | 2021-07-26 21:09:38 +0200 |
| commit | 5d45edbeac143c0a18d82efde92cc5e22c4dc021 (patch) | |
| tree | d4cf302bf80103c7b236da6fff938bbce1dd8bcd /hw/nvme | |
| parent | 5ffbaeed164da1a87619a3abfadee0c7d63ea1c4 (diff) | |
| download | qemu-5d45edbeac143c0a18d82efde92cc5e22c4dc021.zip qemu-5d45edbeac143c0a18d82efde92cc5e22c4dc021.tar.gz qemu-5d45edbeac143c0a18d82efde92cc5e22c4dc021.tar.bz2 | |
hw/nvme: split pmrmsc register into upper and lower
The specification uses a set of 32 bit PMRMSCL and PMRMSCU registers to
make up the 64 bit logical PMRMSC register.
Make it so.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Diffstat (limited to 'hw/nvme')
| -rw-r--r-- | hw/nvme/ctrl.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 2f0524e..070d9f6 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -5916,11 +5916,13 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, return; } - n->bar.pmrmsc = (n->bar.pmrmsc & ~0xffffffff) | (data & 0xffffffff); + n->bar.pmrmscl = data; n->pmr.cmse = false; - if (NVME_PMRMSC_CMSE(n->bar.pmrmsc)) { - hwaddr cba = NVME_PMRMSC_CBA(n->bar.pmrmsc) << PMRMSC_CBA_SHIFT; + if (NVME_PMRMSCL_CMSE(n->bar.pmrmscl)) { + uint64_t pmrmscu = n->bar.pmrmscu; + hwaddr cba = (pmrmscu << 32) | + (NVME_PMRMSCL_CBA(n->bar.pmrmscl) << PMRMSCL_CBA_SHIFT); if (cba + int128_get64(n->pmr.dev->mr.size) < cba) { NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 1); return; @@ -5936,7 +5938,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, return; } - n->bar.pmrmsc = (n->bar.pmrmsc & 0xffffffff) | (data << 32); + n->bar.pmrmscu = data; return; default: NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid, |