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| author | Akihiko Odaki <akihiko.odaki@daynix.com> | 2023-05-23 11:43:36 +0900 |
|---|---|---|
| committer | Jason Wang <jasowang@redhat.com> | 2023-05-23 15:20:15 +0800 |
| commit | efb1fd7a73aac29b02514c8aa46b752a7c7caa73 (patch) | |
| tree | 0f9af6b8bfe29891a3d84bee44d2e11b7554adc8 /hw/net | |
| parent | 5844562b177e2067b8ebf78d1845334e0c759896 (diff) | |
| download | qemu-efb1fd7a73aac29b02514c8aa46b752a7c7caa73.zip qemu-efb1fd7a73aac29b02514c8aa46b752a7c7caa73.tar.gz qemu-efb1fd7a73aac29b02514c8aa46b752a7c7caa73.tar.bz2 | |
igb: Clear-on-read ICR when ICR.INTA is set
For GPIE.NSICR, Section 7.3.2.1.2 says:
> ICR bits are cleared on register read. If GPIE.NSICR = 0b, then the
> clear on read occurs only if no bit is set in the IMS or at least one
> bit is set in the IMS and there is a true interrupt as reflected in
> ICR.INTA.
e1000e does similar though it checks for CTRL_EXT.IAME, which does not
exist on igb.
Suggested-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Diffstat (limited to 'hw/net')
| -rw-r--r-- | hw/net/igb_core.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index 823dde8..d00b1ca 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -2598,6 +2598,8 @@ igb_mac_icr_read(IGBCore *core, int index) } else if (core->mac[IMS] == 0) { trace_e1000e_irq_icr_clear_zero_ims(); igb_lower_interrupts(core, ICR, 0xffffffff); + } else if (core->mac[ICR] & E1000_ICR_INT_ASSERTED) { + igb_lower_interrupts(core, ICR, 0xffffffff); } else if (!msix_enabled(core->owner)) { trace_e1000e_irq_icr_clear_nonmsix_icr_read(); igb_lower_interrupts(core, ICR, 0xffffffff); |