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| author | Akihiko Odaki <akihiko.odaki@daynix.com> | 2023-05-23 11:43:33 +0900 |
|---|---|---|
| committer | Jason Wang <jasowang@redhat.com> | 2023-05-23 15:20:15 +0800 |
| commit | 3dfc616eabc18f036511178bf7551f34abfd19cb (patch) | |
| tree | 6dc189575bb3d89b3d6e976233eddabb21a510e0 /hw/net | |
| parent | 3a9926d939f86243e9fff28b516411236999e3c4 (diff) | |
| download | qemu-3dfc616eabc18f036511178bf7551f34abfd19cb.zip qemu-3dfc616eabc18f036511178bf7551f34abfd19cb.tar.gz qemu-3dfc616eabc18f036511178bf7551f34abfd19cb.tar.bz2 | |
igb: Implement Tx timestamp
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Diffstat (limited to 'hw/net')
| -rw-r--r-- | hw/net/igb_core.c | 7 | ||||
| -rw-r--r-- | hw/net/igb_regs.h | 3 |
2 files changed, 10 insertions, 0 deletions
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c index 43d23c7..49d1917 100644 --- a/hw/net/igb_core.c +++ b/hw/net/igb_core.c @@ -659,6 +659,13 @@ igb_process_tx_desc(IGBCore *core, tx->ctx[idx].vlan_macip_lens >> IGB_TX_FLAGS_VLAN_SHIFT, !!(tx->first_cmd_type_len & E1000_TXD_CMD_VLE)); + if ((tx->first_cmd_type_len & E1000_ADVTXD_MAC_TSTAMP) && + (core->mac[TSYNCTXCTL] & E1000_TSYNCTXCTL_ENABLED) && + !(core->mac[TSYNCTXCTL] & E1000_TSYNCTXCTL_VALID)) { + core->mac[TSYNCTXCTL] |= E1000_TSYNCTXCTL_VALID; + e1000x_timestamp(core->mac, core->timadj, TXSTMPL, TXSTMPH); + } + if (igb_tx_pkt_send(core, tx, queue_index)) { igb_on_tx_done_update_stats(core, tx->tx_pkt, queue_index); } diff --git a/hw/net/igb_regs.h b/hw/net/igb_regs.h index 8947055..82ff195 100644 --- a/hw/net/igb_regs.h +++ b/hw/net/igb_regs.h @@ -322,6 +322,9 @@ union e1000_adv_rx_desc { /* E1000_EITR_CNT_IGNR is only for 82576 and newer */ #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ +#define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */ +#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */ + /* PCI Express Control */ #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 |