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| author | Michael S. Tsirkin <mst@redhat.com> | 2009-11-25 12:00:10 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2009-12-01 18:00:00 +0200 |
| commit | 1f944c661a821774e7b8cfbf5560a238795f2a60 (patch) | |
| tree | 5665679277dac50aaa9eaedf025a1ca954ab38fc /hw/msix.c | |
| parent | ae1be0bbc127a9a6289873efdb7cb22c57d81a9d (diff) | |
| download | qemu-1f944c661a821774e7b8cfbf5560a238795f2a60.zip qemu-1f944c661a821774e7b8cfbf5560a238795f2a60.tar.gz qemu-1f944c661a821774e7b8cfbf5560a238795f2a60.tar.bz2 | |
msix: fix reset value for enable bit
On reset, we currently clear all bits in msix control register *except*
enable bit. This is wrong: the spec says we should clear writeable
bits: function mask and enable bit.
Correct this.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/msix.c')
| -rw-r--r-- | hw/msix.c | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -361,7 +361,8 @@ void msix_reset(PCIDevice *dev) if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) return; msix_free_irq_entries(dev); - dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= MSIX_ENABLE_MASK; + dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= + ~dev->wmask[dev->msix_cap + MSIX_ENABLE_OFFSET]; memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE); msix_mask_all(dev, dev->msix_entries_nr); } |