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| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2015-11-11 22:49:46 +0000 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2015-11-12 13:15:55 +1100 |
| commit | d271ae36dc1e292ae140f5bbf23e0fc1392dd325 (patch) | |
| tree | 0bc6a6c08a9c55e4551ea9605ffd78c4534341c2 /hw/misc | |
| parent | ce8d3b647b5acc2bec19602d9fac87d3da11ae77 (diff) | |
| download | qemu-d271ae36dc1e292ae140f5bbf23e0fc1392dd325.zip qemu-d271ae36dc1e292ae140f5bbf23e0fc1392dd325.tar.gz qemu-d271ae36dc1e292ae140f5bbf23e0fc1392dd325.tar.bz2 | |
cuda.c: fix CUDA SR interrupt clearing
Make sure that we also clear the data and clock interrupts at the same time.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/misc')
| -rw-r--r-- | hw/misc/macio/cuda.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index b7e9dee..364473f 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -57,6 +57,8 @@ #define IER_SET 0x80 /* set bits in IER */ #define IER_CLR 0 /* clear bits in IER */ #define SR_INT 0x04 /* Shift register full/empty */ +#define SR_DATA_INT 0x08 +#define SR_CLOCK_INT 0x10 #define T1_INT 0x40 /* Timer 1 interrupt */ #define T2_INT 0x20 /* Timer 2 interrupt */ @@ -261,7 +263,7 @@ static uint32_t cuda_readb(void *opaque, hwaddr addr) break; case 10: val = s->sr; - s->ifr &= ~SR_INT; + s->ifr &= ~(SR_INT | SR_CLOCK_INT | SR_DATA_INT); cuda_update_irq(s); break; case 11: |