diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2023-02-07 20:13:38 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2023-02-07 20:13:38 +0000 |
commit | 969d09c3a6186c0a4bc8a41db0c1aba1c76081fc (patch) | |
tree | d3809ea9f1a6b64c88562a96c0d4a0882b3b6d55 /hw/misc | |
parent | 5c71a911267f742a71e2c7725dd3164347c61738 (diff) | |
parent | bf81b8f8acda4f1f774adc5f8e76225d472c6ae5 (diff) | |
download | qemu-969d09c3a6186c0a4bc8a41db0c1aba1c76081fc.zip qemu-969d09c3a6186c0a4bc8a41db0c1aba1c76081fc.tar.gz qemu-969d09c3a6186c0a4bc8a41db0c1aba1c76081fc.tar.bz2 |
Merge tag 'pull-aspeed-20230207' of https://github.com/legoater/qemu into staging
aspeed queue:
* various small cleanups and fixes
* new variant of the supermicrox11-bmc machine using an ast2500-a1 SoC
* at24c_eeprom extension to define eeprom contents with static arrays
* ast10x0 model and test improvements
* avocado update of images to use the latest
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmPiByEACgkQUaNDx8/7
# 7KF1nw/7BxVb8bxO5T00AnGDFNahDq3ItyisrbOkElDw18oN1eULrtZFH1UopjDE
# 3HKwR2nb4X7MfcLirVXXxwO1GgIxUkeCsVEY6hpg3TxDPRhPW2toNpNt/WCfFKgq
# ZdYdaKgkON/xHQPv6kgQzU2n9Zpuznj0CE9A3k1mAyBcCSitsvu4TW6AQBKmLgUR
# 9lu61onfX9XoPxZv3abuY3c3UyzevOc6BUT67dmr8naAhHLyBU+DWAW6Kg0Dtc9j
# p+bwxIDRimK50DJt9l13OLSAJyhrW1gMsPPGb+48OClpEOhHwq8oqRuMFpbHaQ0/
# 2MMtMbavXtzBScfmLzR3yw2IwohxSXKMe+7irkJiG/hc8/gtpRATaaS+zfvS0rla
# QybWYtJyjmW+QUOnmBsKGwT0PWJcOd3bKtVPgPd7WGeHGVtTBOqU/svExaO+gIv8
# uX1gOelEgLmLenUjc/Wp4cHgnePTBK8vG1g3IrEtcCblhwpr0e3/aJgHGgO3cQzH
# X9P2buwHyLzjsie9S1ebG9Ceg/VsGQpxNGISZdG+Z4c3+GYu5gcGQcqIAuFmwBnE
# QHSNHJXITyWjo7UuqL7e1J7vROUKn0S15V9MO/yOmZgkqubu4Gt3jGcJtIGqIBlu
# MFra7SiVjKBnt6PD3aKEdD9uahbqFUfmX9411ZmYUUzpfflKnCQ=
# =IY/i
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Feb 2023 08:09:05 GMT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20230207' of https://github.com/legoater/qemu: (25 commits)
aspeed/sdmc: Drop unnecessary scu include
tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board
hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F
hw/arm/aspeed_ast10x0: Map HACE peripheral
hw/arm/aspeed_ast10x0: Map the secure SRAM
hw/arm/aspeed_ast10x0: Map I3C peripheral
hw/arm/aspeed_ast10x0: Add various unimplemented peripherals
hw/misc/aspeed_hace: Do not crash if address_space_map() failed
hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP level
hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers
hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize'
hw/nvram/eeprom_at24c: Make reset behavior more like hardware
hw/arm/aspeed: Add aspeed_eeprom.c
hw/nvram/eeprom_at24c: Add init_rom field and at24c_eeprom_init_rom helper
hw/arm/aspeed: Replace aspeed_eeprom_init with at24c_eeprom_init
hw/arm: Extract at24c_eeprom_init helper from Aspeed and Nuvoton boards
hw/core/loader: Remove declarations of option_rom_has_mr/rom_file_has_mr
tests/avocado/machine_aspeed.py: Mask systemd services to speed up SDK boot
tests/avocado/machine_aspeed.py: update buildroot tests
m25p80: Add the is25wp256 SFPD table
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc')
-rw-r--r-- | hw/misc/aspeed_hace.c | 21 | ||||
-rw-r--r-- | hw/misc/aspeed_sdmc.c | 1 |
2 files changed, 15 insertions, 7 deletions
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index ac21be3..12a761f 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -193,6 +193,7 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, size_t digest_len = 0; int niov = 0; int i; + void *haddr; if (sg_mode) { uint32_t len = 0; @@ -217,9 +218,13 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, addr &= SG_LIST_ADDR_MASK; plen = len & SG_LIST_LEN_MASK; - iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false, - MEMTXATTRS_UNSPECIFIED); - + haddr = address_space_map(&s->dram_as, addr, &plen, false, + MEMTXATTRS_UNSPECIFIED); + if (haddr == NULL) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); + return; + } + iov[i].iov_base = haddr; if (acc_mode) { niov = gen_acc_mode_iov(s, iov, i, &plen); @@ -230,10 +235,14 @@ static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode, } else { hwaddr len = s->regs[R_HASH_SRC_LEN]; + haddr = address_space_map(&s->dram_as, s->regs[R_HASH_SRC], + &len, false, MEMTXATTRS_UNSPECIFIED); + if (haddr == NULL) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); + return; + } + iov[0].iov_base = haddr; iov[0].iov_len = len; - iov[0].iov_base = address_space_map(&s->dram_as, s->regs[R_HASH_SRC], - &len, false, - MEMTXATTRS_UNSPECIFIED); i = 1; if (s->iov_count) { diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index d2a3931..abb2727 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -12,7 +12,6 @@ #include "qemu/module.h" #include "qemu/error-report.h" #include "hw/misc/aspeed_sdmc.h" -#include "hw/misc/aspeed_scu.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "qapi/error.h" |