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author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-03-31 11:59:49 +0200 |
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committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-06-09 09:21:10 +0200 |
commit | 1a5a5570889df9cdd42dd85223e03a5f35025a86 (patch) | |
tree | 80a7d9272e756914fde5629014bf4e9596dd333a /hw/misc/trace-events | |
parent | bb15013ef34617eb1344f5276292cadd326c21b2 (diff) | |
download | qemu-1a5a5570889df9cdd42dd85223e03a5f35025a86.zip qemu-1a5a5570889df9cdd42dd85223e03a5f35025a86.tar.gz qemu-1a5a5570889df9cdd42dd85223e03a5f35025a86.tar.bz2 |
hw/misc/grlib_ahb_apb_pnp: Fix AHB PnP 8-bit accesses
The Plug & Play region of the AHB/APB bridge can be accessed
by various word size, however the implementation is clearly
restricted to 32-bit:
static uint64_t grlib_ahb_pnp_read(void *opaque, hwaddr offset, unsigned size)
{
AHBPnp *ahb_pnp = GRLIB_AHB_PNP(opaque);
return ahb_pnp->regs[offset >> 2];
}
Similarly to commit 0fbe394a64 with the APB PnP registers,
set the MemoryRegionOps::impl min/max fields to 32-bit, so
memory.c::access_with_adjusted_size() can adjust when the
access is not 32-bit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
Message-Id: <20200331105048.27989-4-f4bug@amsat.org>
Diffstat (limited to 'hw/misc/trace-events')
0 files changed, 0 insertions, 0 deletions