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| author | Jean-Philippe Brucker <jean-philippe@linaro.org> | 2023-08-22 17:31:11 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-08-22 17:31:11 +0100 |
| commit | ceaa97465f58cf2b3b4fc07a3b1067eb6f48d2e3 (patch) | |
| tree | 3559a31425ed4aeb648aae6fe5e2ecf23ae5087e /hw/misc/mst_fpga.c | |
| parent | da64251e9317b3937cad54f71f606f5f9b837c8e (diff) | |
| download | qemu-ceaa97465f58cf2b3b4fc07a3b1067eb6f48d2e3.zip qemu-ceaa97465f58cf2b3b4fc07a3b1067eb6f48d2e3.tar.gz qemu-ceaa97465f58cf2b3b4fc07a3b1067eb6f48d2e3.tar.bz2 | |
target/arm/helper: Fix tlbmask and tlbbits for TLBI VAE2*
When HCR_EL2.E2H is enabled, TLB entries are formed using the EL2&0
translation regime, instead of the EL2 translation regime. The TLB VAE2*
instructions invalidate the regime that corresponds to the current value
of HCR_EL2.E2H.
At the moment we only invalidate the EL2 translation regime. This causes
problems with RMM, which issues TLBI VAE2IS instructions with
HCR_EL2.E2H enabled. Update vae2_tlbmask() to take HCR_EL2.E2H into
account.
Add vae2_tlbbits() as well, since the top-byte-ignore configuration is
different between the EL2&0 and EL2 regime.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230809123706.1842548-3-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/mst_fpga.c')
0 files changed, 0 insertions, 0 deletions