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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-03 18:40:20 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:19 -0700 |
| commit | a4b84608ba0eecce1d4858181457dc26582e6d28 (patch) | |
| tree | c657deeba29792d6cda5b76235810d8763cc2497 /hw/misc/meson.build | |
| parent | b609b7e3199912e16ef3b0447823f21fed73597e (diff) | |
| download | qemu-a4b84608ba0eecce1d4858181457dc26582e6d28.zip qemu-a4b84608ba0eecce1d4858181457dc26582e6d28.tar.gz qemu-a4b84608ba0eecce1d4858181457dc26582e6d28.tar.bz2 | |
hw/riscv: Move sifive_test model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_test model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/meson.build')
| -rw-r--r-- | hw/misc/meson.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 018a88c..bd24132 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) # RISC-V devices +softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c')) |