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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-10-12 11:57:59 +0200
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2020-10-17 13:59:40 +0200
commit79b99fe3f09979b6ba0a8d9f4603dc43e7e066c4 (patch)
treec75ac7bee41e66b08ffb2efc8068b02227020950 /hw/mips
parent8543a806912da7cdbc45303226762372f92f689b (diff)
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hw/mips/jazz: Correct CPU frequencies
The Magnum 4000PC CPU runs at 100 MHz, and the Acer PICA-61 CPU at ~134 MHz. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-17-f4bug@amsat.org>
Diffstat (limited to 'hw/mips')
-rw-r--r--hw/mips/jazz.c15
1 files changed, 14 insertions, 1 deletions
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index 4772309..8f1ad55 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
+#include "hw/clock.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
#include "hw/intc/i8259.h"
@@ -142,6 +143,7 @@ static void mips_jazz_init(MachineState *machine,
MemoryRegion *address_space = get_system_memory();
char *filename;
int bios_size, n;
+ Clock *cpuclk;
MIPSCPU *cpu;
CPUClass *cc;
CPUMIPSState *env;
@@ -163,14 +165,25 @@ static void mips_jazz_init(MachineState *machine,
MemoryRegion *bios2 = g_new(MemoryRegion, 1);
SysBusESPState *sysbus_esp;
ESPState *esp;
+ static const struct {
+ unsigned freq_hz;
+ unsigned pll_mult;
+ } ext_clk[] = {
+ [JAZZ_MAGNUM] = {50000000, 2},
+ [JAZZ_PICA61] = {33333333, 4},
+ };
if (machine->ram_size > 256 * MiB) {
error_report("RAM size more than 256Mb is not supported");
exit(EXIT_FAILURE);
}
+ cpuclk = clock_new(OBJECT(machine), "cpu-refclk");
+ clock_set_hz(cpuclk, ext_clk[jazz_model].freq_hz
+ * ext_clk[jazz_model].pll_mult);
+
/* init CPUs */
- cpu = MIPS_CPU(cpu_create(machine->cpu_type));
+ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);