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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-01-13 09:20:12 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-01-13 09:32:32 +0100 |
| commit | a7db759ef70fdc6ec7e79c603d3daf7c87113bba (patch) | |
| tree | 0d5014e40f10b5cd97ec9726712d13a6616120d1 /hw/mips/trace-events | |
| parent | 90f7d0b4940be29259f6977d2df2ca09495680e7 (diff) | |
| download | qemu-a7db759ef70fdc6ec7e79c603d3daf7c87113bba.zip qemu-a7db759ef70fdc6ec7e79c603d3daf7c87113bba.tar.gz qemu-a7db759ef70fdc6ec7e79c603d3daf7c87113bba.tar.bz2 | |
hw/mips/gt64xxx_pci: Move it to hw/pci-host/
The GT-64120 is a north-bridge, and it is not MIPS specific.
Move it with the other north-bridge devices.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20221209151533.69516-8-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/mips/trace-events')
| -rw-r--r-- | hw/mips/trace-events | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/hw/mips/trace-events b/hw/mips/trace-events index b5b882c..4a4e5fe 100644 --- a/hw/mips/trace-events +++ b/hw/mips/trace-events @@ -1,10 +1,3 @@ -# gt64xxx_pci.c -gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64 -gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64 -gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 -gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 -gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 - # malta.c malta_fpga_leds(const char *text) "LEDs %s" malta_fpga_display(const char *text) "ASCII '%s'" |