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author | Peter Maydell <peter.maydell@linaro.org> | 2019-08-20 13:40:48 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2019-08-20 13:40:48 +0100 |
commit | bbd69d36d173d28a9af9298f1c5433f8c07f49c5 (patch) | |
tree | e91a545aa500c1c295f5679a4ada1671c62f6703 /hw/mips/cps.c | |
parent | 156d320349df5d17e1c4fbf11fad70d2d93f5e26 (diff) | |
parent | 6eed53f71b33c3716e5d94eba506e4706d8dace8 (diff) | |
download | qemu-bbd69d36d173d28a9af9298f1c5433f8c07f49c5.zip qemu-bbd69d36d173d28a9af9298f1c5433f8c07f49c5.tar.gz qemu-bbd69d36d173d28a9af9298f1c5433f8c07f49c5.tar.bz2 |
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-20-2019' into staging
MIPS queue for August 20th, 2019
# gpg: Signature made Mon 19 Aug 2019 19:07:18 BST
# gpg: using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65
* remotes/amarkovic/tags/mips-queue-aug-20-2019:
target/mips: tests/tcg: Fix target configurations for MSA tests
target/mips: tests/tcg: Add optional printing of more detailed failure info
target/mips: Style improvements in mips_mipssim.c
target/mips: Style improvements in mips_malta.c
target/mips: Style improvements in mips_int.c
target/mips: Style improvements in mips_fulong2e.c
target/mips: Style improvements in cps.c
target/mips: Style improvements in translate.c
target/mips: Style improvements in machine.c
target/mips: Style improvements in cpu.c
target/mips: Style improvements in cp0_timer.c
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/mips/cps.c')
-rw-r--r-- | hw/mips/cps.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/hw/mips/cps.c b/hw/mips/cps.c index cd8b07d..1660f86 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -38,8 +38,10 @@ static void mips_cps_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); MIPSCPSState *s = MIPS_CPS(obj); - /* Cover entire address space as there do not seem to be any - * constraints for the base address of CPC and GIC. */ + /* + * Cover entire address space as there do not seem to be any + * constraints for the base address of CPC and GIC. + */ memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX); sysbus_init_mmio(sbd, &s->container); } |