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| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-09-23 17:18:35 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2022-10-09 16:38:45 -0400 |
| commit | 9c769e04465118601dea96b02c27887bd46cce25 (patch) | |
| tree | 89d6337823316e3ff130de8329f5ba897da53ae6 /hw/mem | |
| parent | 0a17270761e7d90a67edadb19c7f6871387931be (diff) | |
| download | qemu-9c769e04465118601dea96b02c27887bd46cce25.zip qemu-9c769e04465118601dea96b02c27887bd46cce25.tar.gz qemu-9c769e04465118601dea96b02c27887bd46cce25.tar.bz2 | |
mem/cxl-type3: Add sn option to provide serial number for PCI ecap
The Device Serial Number Extended Capability PCI r6.0 sec 7.9.3
provides a standard way to provide a device serial number as
an IEEE defined 64-bit extended unique identifier EUI-64.
CXL 2.0 section 8.1.12.2 Memory Device PCIe Capabilities and
Extended Capabilities requires this to be used to uniquely
identify CXL memory devices.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220923161835.9805-1-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Ben Widawsky <bwidawsk@kernel.org>
Diffstat (limited to 'hw/mem')
| -rw-r--r-- | hw/mem/cxl_type3.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index ada2108..a71bf1a 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -14,6 +14,12 @@ #include "sysemu/hostmem.h" #include "hw/cxl/cxl.h" +/* + * Null value of all Fs suggested by IEEE RA guidelines for use of + * EU, OUI and CID + */ +#define UI64_NULL ~(0ULL) + static void build_dvsecs(CXLType3Dev *ct3d) { CXLComponentState *cxl_cstate = &ct3d->cxl_cstate; @@ -149,7 +155,12 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL); pcie_endpoint_cap_init(pci_dev, 0x80); - cxl_cstate->dvsec_offset = 0x100; + if (ct3d->sn != UI64_NULL) { + pcie_dev_ser_num_init(pci_dev, 0x100, ct3d->sn); + cxl_cstate->dvsec_offset = 0x100 + 0x0c; + } else { + cxl_cstate->dvsec_offset = 0x100; + } ct3d->cxl_cstate.pdev = pci_dev; build_dvsecs(ct3d); @@ -275,6 +286,7 @@ static Property ct3_props[] = { HostMemoryBackend *), DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND, HostMemoryBackend *), + DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL), DEFINE_PROP_END_OF_LIST(), }; |