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| author | malc <av1474@comtv.ru> | 2009-10-01 22:20:47 +0400 |
|---|---|---|
| committer | malc <av1474@comtv.ru> | 2009-10-01 22:45:02 +0400 |
| commit | 99a0949b720a0936da2052cb9a46db04ffc6db29 (patch) | |
| tree | f9e39633853e35b49fc4465337cc196b9650866e /hw/isa_mmio.c | |
| parent | bc6291a1b95a2c4c546fde6e5cb4c68366f06649 (diff) | |
| download | qemu-99a0949b720a0936da2052cb9a46db04ffc6db29.zip qemu-99a0949b720a0936da2052cb9a46db04ffc6db29.tar.gz qemu-99a0949b720a0936da2052cb9a46db04ffc6db29.tar.bz2 | |
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.
Signed-off-by: malc <av1474@comtv.ru>
Diffstat (limited to 'hw/isa_mmio.c')
| -rw-r--r-- | hw/isa_mmio.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c index ed0e189..6a1967b 100644 --- a/hw/isa_mmio.c +++ b/hw/isa_mmio.c @@ -25,13 +25,13 @@ #include "hw.h" #include "isa.h" -static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr, +static void isa_mmio_writeb (void *opaque, a_target_phys_addr addr, uint32_t val) { cpu_outb(addr & IOPORTS_MASK, val); } -static void isa_mmio_writew (void *opaque, target_phys_addr_t addr, +static void isa_mmio_writew (void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN @@ -40,7 +40,7 @@ static void isa_mmio_writew (void *opaque, target_phys_addr_t addr, cpu_outw(addr & IOPORTS_MASK, val); } -static void isa_mmio_writel (void *opaque, target_phys_addr_t addr, +static void isa_mmio_writel (void *opaque, a_target_phys_addr addr, uint32_t val) { #ifdef TARGET_WORDS_BIGENDIAN @@ -49,7 +49,7 @@ static void isa_mmio_writel (void *opaque, target_phys_addr_t addr, cpu_outl(addr & IOPORTS_MASK, val); } -static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr) +static uint32_t isa_mmio_readb (void *opaque, a_target_phys_addr addr) { uint32_t val; @@ -57,7 +57,7 @@ static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr) return val; } -static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr) +static uint32_t isa_mmio_readw (void *opaque, a_target_phys_addr addr) { uint32_t val; @@ -68,7 +68,7 @@ static uint32_t isa_mmio_readw (void *opaque, target_phys_addr_t addr) return val; } -static uint32_t isa_mmio_readl (void *opaque, target_phys_addr_t addr) +static uint32_t isa_mmio_readl (void *opaque, a_target_phys_addr addr) { uint32_t val; @@ -93,7 +93,7 @@ static CPUReadMemoryFunc * const isa_mmio_read[] = { static int isa_mmio_iomemtype = 0; -void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size) +void isa_mmio_init(a_target_phys_addr base, a_target_phys_addr size) { if (!isa_mmio_iomemtype) { isa_mmio_iomemtype = cpu_register_io_memory(isa_mmio_read, |