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authorBALATON Zoltan <balaton@eik.bme.hu>2023-02-16 21:21:35 +0100
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2023-03-08 00:37:48 +0100
commit2fdadd02e675caca4aba4ae26317701fe2c4c901 (patch)
treeeb1b64a8cfbb51f7f9de6cf0db90b564a8905305 /hw/isa/vt82c686.c
parentecb0e98b4f24495dd4febab7d69579d62773bdc4 (diff)
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hw/isa/vt82c686: Implement PCI IRQ routing
The real VIA south bridges implement a PCI IRQ router which is configured by the BIOS or the OS. In order to respect these configurations, QEMU needs to implement it as well. The real chip may allow routing IRQs from internal functions independently of PCI interrupts but since guests usually configute it to a single shared interrupt we don't model that here for simplicity. Note: The implementation was taken from piix4_set_irq() in hw/isa/piix4. Suggested-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Message-Id: <fbb016c7d0e19093335c237e15f5f6c62c4393b4.1678188711.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'hw/isa/vt82c686.c')
-rw-r--r--hw/isa/vt82c686.c42
1 files changed, 42 insertions, 0 deletions
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 01e0148..71da316 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -604,6 +604,46 @@ static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
qemu_set_irq(s->cpu_intr, level);
}
+static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num)
+{
+ switch (irq_num) {
+ case 0:
+ return s->dev.config[0x55] >> 4;
+ case 1:
+ return s->dev.config[0x56] & 0xf;
+ case 2:
+ return s->dev.config[0x56] >> 4;
+ case 3:
+ return s->dev.config[0x57] >> 4;
+ }
+ return 0;
+}
+
+static void via_isa_set_pci_irq(void *opaque, int irq_num, int level)
+{
+ ViaISAState *s = opaque;
+ PCIBus *bus = pci_get_bus(&s->dev);
+ int i, pic_level, pic_irq = via_isa_get_pci_irq(s, irq_num);
+
+ /* IRQ 0: disabled, IRQ 2,8,13: reserved */
+ if (!pic_irq) {
+ return;
+ }
+ if (unlikely(pic_irq == 2 || pic_irq == 8 || pic_irq == 13)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing");
+ }
+
+ /* The pic level is the logical OR of all the PCI irqs mapped to it. */
+ pic_level = 0;
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ if (pic_irq == via_isa_get_pci_irq(s, i)) {
+ pic_level |= pci_bus_get_irq_level(bus, i);
+ }
+ }
+ /* Now we change the pic irq level according to the via irq mappings. */
+ qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level);
+}
+
static void via_isa_realize(PCIDevice *d, Error **errp)
{
ViaISAState *s = VIA_ISA(d);
@@ -627,6 +667,8 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
i8254_pit_init(isa_bus, 0x40, 0, NULL);
i8257_dma_init(isa_bus, 0);
+ qdev_init_gpio_in_named(dev, via_isa_set_pci_irq, "pirq", PCI_NUM_PINS);
+
/* RTC */
qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {