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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-09-10 18:38:52 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-10-01 15:31:00 +0100 |
| commit | 8a130a7be6e222965641e1fd9469fd3ee752c7d4 (patch) | |
| tree | e6074a5fcc454d3b17ee061b995f66300568abfe /hw/intc | |
| parent | 0ae0326b984e77a55c224b7863071bd3d8951231 (diff) | |
| download | qemu-8a130a7be6e222965641e1fd9469fd3ee752c7d4.zip qemu-8a130a7be6e222965641e1fd9469fd3ee752c7d4.tar.gz qemu-8a130a7be6e222965641e1fd9469fd3ee752c7d4.tar.bz2 | |
target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters
sub-struct. We're going to want id_pfr1 for an isar_features
check, and moving both at the same time avoids an odd
inconsistency.
Changes other than the ones to cpu.h and kvm64.c made
automatically with:
perl -p -i -e 's/cpu->id_pfr/cpu->isar.id_pfr/' target/arm/*.c hw/intc/armv7m_nvic.c
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-3-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 7876c1b..a28be49 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1238,9 +1238,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) "Aux Fault status registers unimplemented\n"); return 0; case 0xd40: /* PFR0. */ - return cpu->id_pfr0; + return cpu->isar.id_pfr0; case 0xd44: /* PFR1. */ - return cpu->id_pfr1; + return cpu->isar.id_pfr1; case 0xd48: /* DFR0. */ return cpu->isar.id_dfr0; case 0xd4c: /* AFR0. */ |