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author | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:39 +0100 |
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committer | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:39 +0100 |
commit | c6b8cc370d2ccb1a6e89df9329f2ef8f77d1d664 (patch) | |
tree | c96c7035f0de8f12cf38921f45ff7c8c93a6559f /hw/intc | |
parent | 0aa2612a01f233a4a25fb89e8362baf6cf896be6 (diff) | |
download | qemu-c6b8cc370d2ccb1a6e89df9329f2ef8f77d1d664.zip qemu-c6b8cc370d2ccb1a6e89df9329f2ef8f77d1d664.tar.gz qemu-c6b8cc370d2ccb1a6e89df9329f2ef8f77d1d664.tar.bz2 |
ppc/pnv: Add support for PQ offload on PHB5
The PQ_disable configuration bit disables the check done on the PQ
state bits when processing new MSI interrupts. When bit 9 is enabled,
the PHB forwards any MSI trigger to the XIVE interrupt controller
without checking the PQ state bits. The XIVE IC knows from the trigger
message that the PQ bits have not been checked and performs the check
locally.
This configuration bit only applies to MSIs and LSIs are still checked
on the PHB to handle the assertion level.
PQ_disable enablement is a requirement for StoreEOI.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw/intc')
-rw-r--r-- | hw/intc/xive.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/hw/intc/xive.c b/hw/intc/xive.c index deb0db2..b8e4c72 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -887,6 +887,16 @@ static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno) } /* + * Sources can be configured with PQ offloading in which case the check + * on the PQ state bits of MSIs is disabled + */ +static bool xive_source_esb_disabled(XiveSource *xsrc, uint32_t srcno) +{ + return (xsrc->esb_flags & XIVE_SRC_PQ_DISABLE) && + !xive_source_irq_is_lsi(xsrc, srcno); +} + +/* * Returns whether the event notification should be forwarded. */ static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) @@ -895,6 +905,10 @@ static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno) assert(srcno < xsrc->nr_irqs); + if (xive_source_esb_disabled(xsrc, srcno)) { + return true; + } + ret = xive_esb_trigger(&xsrc->status[srcno]); if (xive_source_irq_is_lsi(xsrc, srcno) && @@ -915,6 +929,11 @@ static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) assert(srcno < xsrc->nr_irqs); + if (xive_source_esb_disabled(xsrc, srcno)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EOI for IRQ %d\n", srcno); + return false; + } + ret = xive_esb_eoi(&xsrc->status[srcno]); /* @@ -936,9 +955,10 @@ static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno) static void xive_source_notify(XiveSource *xsrc, int srcno) { XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive); + bool pq_checked = !xive_source_esb_disabled(xsrc, srcno); if (xnc->notify) { - xnc->notify(xsrc->xive, srcno, true); + xnc->notify(xsrc->xive, srcno, pq_checked); } } |