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| author | Bin Meng <bmeng.cn@gmail.com> | 2021-09-18 11:26:51 +0800 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2021-09-30 12:26:06 +1000 |
| commit | 457279cb49d343b2c39a9efd2b28fe0fbde71f78 (patch) | |
| tree | d40b60f016969167993c20490c3d5fb8f6418cdb /hw/intc | |
| parent | 4d9b8ef9b5ab880d491b0c41d222b42ed83bdbfe (diff) | |
| download | qemu-457279cb49d343b2c39a9efd2b28fe0fbde71f78.zip qemu-457279cb49d343b2c39a9efd2b28fe0fbde71f78.tar.gz qemu-457279cb49d343b2c39a9efd2b28fe0fbde71f78.tar.bz2 | |
hw/intc: openpic: Correct the reset value of IPIDR for FSL chipset
The reset value of IPIDR should be zero for Freescale chipset, per
the following 2 manuals I checked:
- P2020RM (https://www.nxp.com/webapp/Download?colCode=P2020RM)
- P4080RM (https://www.nxp.com/webapp/Download?colCode=P4080RM)
Currently it is set to 1, which leaves the IPI enabled on core 0
after power-on reset. Such may cause unexpected interrupt to be
delivered to core 0 if the IPI is triggered from core 0 to other
cores later.
Fixes: ffd5e9fe0276 ("openpic: Reset IRQ source private members")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/584
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20210918032653.646370-1-bin.meng@windriver.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/openpic.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 9b4c178..2790c67 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -1276,6 +1276,15 @@ static void openpic_reset(DeviceState *d) break; } + /* Mask all IPI interrupts for Freescale OpenPIC */ + if ((opp->model == OPENPIC_MODEL_FSL_MPIC_20) || + (opp->model == OPENPIC_MODEL_FSL_MPIC_42)) { + if (i >= opp->irq_ipi0 && i < opp->irq_tim0) { + write_IRQreg_idr(opp, i, 0); + continue; + } + } + write_IRQreg_idr(opp, i, opp->idr_reset); } /* Initialise IRQ destinations */ |