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authorPeter Maydell <peter.maydell@linaro.org>2017-11-03 18:13:33 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-11-20 13:39:48 +0000
commit2b75ef01caf74be5af964f97e37f07ff9034fe0b (patch)
tree039581265421e04c4c6ecbd130248b4607e7e903 /hw/intc
parent96a8b92ed8f02d5e86ad380d3299d9f41f99b072 (diff)
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nvic: Fix ARMv7M MPU_RBAR reads
Fix an incorrect mask expression in the handling of v7M MPU_RBAR reads that meant that we would always report the ADDR field as zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1509732813-22957-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc')
-rw-r--r--hw/intc/armv7m_nvic.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index be46639..5d9c883 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -977,7 +977,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (region >= cpu->pmsav7_dregion) {
return 0;
}
- return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf);
+ return (cpu->env.pmsav7.drbar[region] & ~0x1f) | (region & 0xf);
}
case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */