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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-01-22 18:24:39 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-01-28 14:29:47 +0000 |
| commit | 1611956bce06b0721ea949e24c089ef22967672a (patch) | |
| tree | f46ff64a87548e4e64a71eaddc6e4d6c0092ad57 /hw/intc/gicv3_internal.h | |
| parent | d7d19c0aeb7d657c76c88913744ff53fc7e24c23 (diff) | |
| download | qemu-1611956bce06b0721ea949e24c089ef22967672a.zip qemu-1611956bce06b0721ea949e24c089ef22967672a.tar.gz qemu-1611956bce06b0721ea949e24c089ef22967672a.tar.bz2 | |
hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported
The GICR_CTLR.CES bit is a read-only bit which is set to 1 to indicate
that the GICR_CTLR.EnableLPIs bit can be written to 0 to disable
LPIs (as opposed to allowing LPIs to be enabled but not subsequently
disabled). Our implementation permits this, so advertise it
by setting CES to 1.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-10-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/gicv3_internal.h')
| -rw-r--r-- | hw/intc/gicv3_internal.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 5394266..a316f6c 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -110,6 +110,7 @@ #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) #define GICR_CTLR_ENABLE_LPIS (1U << 0) +#define GICR_CTLR_CES (1U << 1) #define GICR_CTLR_RWP (1U << 3) #define GICR_CTLR_DPG0 (1U << 24) #define GICR_CTLR_DPG1NS (1U << 25) |