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| author | Peter Maydell <peter.maydell@linaro.org> | 2020-02-14 17:51:03 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-02-21 16:07:01 +0000 |
| commit | a617953855b65a602d36364b9643f7e5bc31288e (patch) | |
| tree | 9b8ef04fc4e905cbfc69a549722b15795e79e37a /hw/intc/armv7m_nvic.c | |
| parent | d52c061e541982a3663ad5c65bd3b518dbe85b87 (diff) | |
| download | qemu-a617953855b65a602d36364b9643f7e5bc31288e.zip qemu-a617953855b65a602d36364b9643f7e5bc31288e.tar.gz qemu-a617953855b65a602d36364b9643f7e5bc31288e.tar.bz2 | |
target/arm: Define an aa32_pmu_8_1 isar feature test function
Instead of open-coding a check on the ID_DFR0 PerfMon ID register
field, create a standardly-named isar_feature for "does AArch32 have
a v8.1 PMUv3" and use it.
This entails moving the id_dfr0 field into the ARMISARegisters struct.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200214175116.9164-9-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/armv7m_nvic.c')
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index f9e0eea..5a403fc 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1227,7 +1227,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) case 0xd44: /* PFR1. */ return cpu->id_pfr1; case 0xd48: /* DFR0. */ - return cpu->id_dfr0; + return cpu->isar.id_dfr0; case 0xd4c: /* AFR0. */ return cpu->id_afr0; case 0xd50: /* MMFR0. */ |