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| author | Christoffer Dall <christoffer.dall@linaro.org> | 2013-09-12 22:18:20 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-08 14:50:48 +0000 |
| commit | aa7d461ae9dd79d35999f4710743cdf9dec88cef (patch) | |
| tree | 8860063b9851b5f786eab320ae33283b4acb327b /hw/intc/arm_gic.c | |
| parent | 40d225009efe17cad647b4b7424b77a3ace232f1 (diff) | |
| download | qemu-aa7d461ae9dd79d35999f4710743cdf9dec88cef.zip qemu-aa7d461ae9dd79d35999f4710743cdf9dec88cef.tar.gz qemu-aa7d461ae9dd79d35999f4710743cdf9dec88cef.tar.bz2 | |
arm_gic: Support setting/getting binary point reg
Add a binary_point field to the gic emulation structure and support
setting/getting this register now when we have it. We don't actually
support interrupt grouping yet, oh well.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/arm_gic.c')
| -rw-r--r-- | hw/intc/arm_gic.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 6550292..5413a24 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -669,14 +669,15 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) case 0x04: /* Priority mask */ return s->priority_mask[cpu]; case 0x08: /* Binary Point */ - /* ??? Not implemented. */ - return 0; + return s->bpr[cpu]; case 0x0c: /* Acknowledge */ return gic_acknowledge_irq(s, cpu); case 0x14: /* Running Priority */ return s->running_priority[cpu]; case 0x18: /* Highest Pending Interrupt */ return s->current_pending[cpu]; + case 0x1c: /* Aliased Binary Point */ + return s->abpr[cpu]; default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_read: Bad offset %x\n", (int)offset); @@ -695,10 +696,15 @@ static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) s->priority_mask[cpu] = (value & 0xff); break; case 0x08: /* Binary Point */ - /* ??? Not implemented. */ + s->bpr[cpu] = (value & 0x7); break; case 0x10: /* End Of Interrupt */ return gic_complete_irq(s, cpu, value & 0x3ff); + case 0x1c: /* Aliased Binary Point */ + if (s->revision >= 2) { + s->abpr[cpu] = (value & 0x7); + } + break; default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_write: Bad offset %x\n", (int)offset); |