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| author | Zhao Liu <zhao1.liu@intel.com> | 2024-04-24 23:49:20 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-05-22 19:43:29 +0200 |
| commit | 81c392ab5c7489955d7e2b515b7186a4cd174c71 (patch) | |
| tree | 89a11c8144ab2f720d1407cc2c92216979095964 /hw/i386 | |
| parent | 822bce9f58df7ab46f70abc9c350341d5280c91a (diff) | |
| download | qemu-81c392ab5c7489955d7e2b515b7186a4cd174c71.zip qemu-81c392ab5c7489955d7e2b515b7186a4cd174c71.tar.gz qemu-81c392ab5c7489955d7e2b515b7186a4cd174c71.tar.bz2 | |
i386: Introduce module level cpu topology to CPUX86State
Intel CPUs implement module level on hybrid client products (e.g.,
ADL-N, MTL, etc) and E-core server products.
A module contains a set of cores that share certain resources (in
current products, the resource usually includes L2 cache, as well as
module scoped features and MSRs).
Module level support is the prerequisite for L2 cache topology on
module level. With module level, we can implement the Guest's CPU
topology and future cache topology to be consistent with the Host's on
Intel hybrid client/E-core server platforms.
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Co-developed-by: Zhuocheng Ding <zhuocheng.ding@intel.com>
Signed-off-by: Zhuocheng Ding <zhuocheng.ding@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Message-ID: <20240424154929.1487382-13-zhao1.liu@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/i386')
| -rw-r--r-- | hw/i386/x86-common.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c index 7d4f9b2..994f842 100644 --- a/hw/i386/x86-common.c +++ b/hw/i386/x86-common.c @@ -271,6 +271,11 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, init_topo_info(&topo_info, x86ms); + if (ms->smp.modules > 1) { + env->nr_modules = ms->smp.modules; + /* TODO: Expose module level in CPUID[0x1F]. */ + } + if (ms->smp.dies > 1) { env->nr_dies = ms->smp.dies; set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo); |