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| author | Roman Artemev <roman.artemev@syntacore.com> | 2024-12-11 07:40:04 +0000 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2024-12-13 15:51:47 +0300 |
| commit | 86f0cfa0efd13eae38d78eee953f24017f5cdb89 (patch) | |
| tree | daf268b221ce81796576b0d5d68903994163927c /hw/i386/x86-common.c | |
| parent | edda3647371c66dcb2922840a684a426b788b983 (diff) | |
| download | qemu-86f0cfa0efd13eae38d78eee953f24017f5cdb89.zip qemu-86f0cfa0efd13eae38d78eee953f24017f5cdb89.tar.gz qemu-86f0cfa0efd13eae38d78eee953f24017f5cdb89.tar.bz2 | |
tcg/riscv: Fix StoreStore barrier generation
On RISC-V to StoreStore barrier corresponds
`fence w, w` not `fence r, r`
Cc: qemu-stable@nongnu.org
Fixes: efbea94c76b ("tcg/riscv: Add slowpath load and store instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Denis Tomashev <denis.tomashev@syntacore.com>
Signed-off-by: Roman Artemev <roman.artemev@syntacore.com>
Message-ID: <e2f2131e294a49e79959d4fa9ec02cf4@syntacore.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
(cherry picked from commit b438362a142527b97b638b7f0f35ebe11911a8d5)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'hw/i386/x86-common.c')
0 files changed, 0 insertions, 0 deletions