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| author | Roman Kapl <rka@sysgo.com> | 2021-04-27 13:05:04 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2021-05-14 10:26:18 -0400 |
| commit | e526ab61e95059e4eaec636bfdedbf6695347cb2 (patch) | |
| tree | b64d32d62c636046f043e2057793b811817c1cbc /hw/i386/amd_iommu.c | |
| parent | ad6461ad6eb3cf36c5d535da5f036f75dd145bcd (diff) | |
| download | qemu-e526ab61e95059e4eaec636bfdedbf6695347cb2.zip qemu-e526ab61e95059e4eaec636bfdedbf6695347cb2.tar.gz qemu-e526ab61e95059e4eaec636bfdedbf6695347cb2.tar.bz2 | |
amd_iommu: fix wrong MMIO operations
Address was swapped with value when writing MMIO registers, so the user
saw garbage in lot of cases. The interrupt status was not correctly set.
Signed-off-by: Roman Kapl <rka@sysgo.com>
Message-Id: <20210427110504.10878-1-rka@sysgo.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/i386/amd_iommu.c')
| -rw-r--r-- | hw/i386/amd_iommu.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 43b6e9b..2801dff 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -99,7 +99,7 @@ static uint64_t amdvi_readq(AMDVIState *s, hwaddr addr) } /* internal write */ -static void amdvi_writeq_raw(AMDVIState *s, uint64_t val, hwaddr addr) +static void amdvi_writeq_raw(AMDVIState *s, hwaddr addr, uint64_t val) { stq_le_p(&s->mmior[addr], val); } @@ -382,7 +382,7 @@ static void amdvi_completion_wait(AMDVIState *s, uint64_t *cmd) } /* set completion interrupt */ if (extract64(cmd[0], 1, 1)) { - amdvi_test_mask(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_COMP_INT); + amdvi_assign_orq(s, AMDVI_MMIO_STATUS, AMDVI_MMIO_STATUS_COMP_INT); /* generate interrupt */ amdvi_generate_msi_interrupt(s); } @@ -553,7 +553,7 @@ static void amdvi_cmdbuf_run(AMDVIState *s) trace_amdvi_command_exec(s->cmdbuf_head, s->cmdbuf_tail, s->cmdbuf); amdvi_cmdbuf_exec(s); s->cmdbuf_head += AMDVI_COMMAND_SIZE; - amdvi_writeq_raw(s, s->cmdbuf_head, AMDVI_MMIO_COMMAND_HEAD); + amdvi_writeq_raw(s, AMDVI_MMIO_COMMAND_HEAD, s->cmdbuf_head); /* wrap head pointer */ if (s->cmdbuf_head >= s->cmdbuf_len * AMDVI_COMMAND_SIZE) { |