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| author | Sven Schnelle <svens@stackframe.org> | 2019-02-18 19:33:14 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-02-21 10:16:19 -0800 |
| commit | 368bec88d1916f65050be305f88c10a46075a51c (patch) | |
| tree | 839e101ad53cb0f5d0c08219e4592ccfcd138e0f /hw/hppa | |
| parent | fc3dbb90f2eb069801bfb4cfe9cbc83cf9c5f4a9 (diff) | |
| download | qemu-368bec88d1916f65050be305f88c10a46075a51c.zip qemu-368bec88d1916f65050be305f88c10a46075a51c.tar.gz qemu-368bec88d1916f65050be305f88c10a46075a51c.tar.bz2 | |
hw/hppa/dino: mask out lower 2 bits of PCI config addr
some versions of HP-UX 10.20 seems to rely on the fact that DINO
strips out the lower 2 bits of the PCI configuration address.
Also update the binary SeaBIOS distributed to the latest version
from Helge's repository, which is required with that change.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Message-Id: <20190218183314.20157-1-svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/hppa')
| -rw-r--r-- | hw/hppa/dino.c | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c index 360716d..40f9e1a 100644 --- a/hw/hppa/dino.c +++ b/hw/hppa/dino.c @@ -178,7 +178,7 @@ static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr, case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3: /* Read from PCI IO space. */ io = &address_space_io; - ioaddr = s->parent_obj.config_reg; + ioaddr = s->parent_obj.config_reg + (addr & 3); switch (size) { case 1: val = address_space_ldub(io, ioaddr, attrs, &ret); @@ -250,7 +250,7 @@ static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr, case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3: /* Write into PCI IO space. */ io = &address_space_io; - ioaddr = s->parent_obj.config_reg; + ioaddr = s->parent_obj.config_reg + (addr & 3); switch (size) { case 1: address_space_stb(io, ioaddr, val, attrs, &ret); @@ -360,6 +360,27 @@ static const MemoryRegionOps dino_config_data_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; +static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len) +{ + PCIHostState *s = opaque; + return s->config_reg; +} + +static void dino_config_addr_write(void *opaque, hwaddr addr, + uint64_t val, unsigned len) +{ + PCIHostState *s = opaque; + s->config_reg = val & ~3U; +} + +static const MemoryRegionOps dino_config_addr_ops = { + .read = dino_config_addr_read, + .write = dino_config_addr_write, + .valid.min_access_size = 4, + .valid.max_access_size = 4, + .endianness = DEVICE_BIG_ENDIAN, +}; + static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque, int devfn) { @@ -440,7 +461,7 @@ PCIBus *dino_init(MemoryRegion *addr_space, /* Dino PCI config. */ memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj), - &pci_host_conf_be_ops, dev, "pci-conf-idx", 4); + &dino_config_addr_ops, dev, "pci-conf-idx", 4); memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj), &dino_config_data_ops, dev, "pci-conf-data", 4); memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR, |