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| author | Helge Deller <deller@gmx.de> | 2019-03-15 17:41:30 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-03-15 10:11:16 -0700 |
| commit | 2b42f31eae2c24507c38326b3534cd9292e7dfcf (patch) | |
| tree | fcb6eaa61ab3b88fc4bbf29c969c9be3dad147e6 /hw/hppa | |
| parent | c5d0aec25f48ac708ad486f84a73e8b622d5b96b (diff) | |
| download | qemu-2b42f31eae2c24507c38326b3534cd9292e7dfcf.zip qemu-2b42f31eae2c24507c38326b3534cd9292e7dfcf.tar.gz qemu-2b42f31eae2c24507c38326b3534cd9292e7dfcf.tar.bz2 | |
Update seabios-hppa to latest upstream
This patch fixes two issues in the hppa/parisc emulation:
1. The CPU HPA was wrong in the sense that we had negative module
offsets in the firmware-internal module table (which we ignored up to
now). Get it correct by changing the CPU HPA to 0xfffb0000 which is
greater than the DINO_HPA of 0xfff80000.
This change requires the seabios-firmware update.
2. Sven noticed that the FPU register cr10 is only able to reference up
to 8 FPUs, so let's reduce the maximum amount of SMP CPUs too.
Signed-off-by: Helge Deller <deller@gmx.de>
Message-Id: <20190315164130.GA7800@ls3530>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'hw/hppa')
| -rw-r--r-- | hw/hppa/hppa_hardware.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/hppa/hppa_hardware.h b/hw/hppa/hppa_hardware.h index 2c61b1f..af2f5ee 100644 --- a/hw/hppa/hppa_hardware.h +++ b/hw/hppa/hppa_hardware.h @@ -19,7 +19,7 @@ #define LASI_PS2KBD_HPA 0xffd08000 #define LASI_PS2MOU_HPA 0xffd08100 #define LASI_GFX_HPA 0xf8000000 -#define CPU_HPA 0xfff10000 +#define CPU_HPA 0xfffb0000 #define MEMORY_HPA 0xfffbf000 #define PCI_HPA DINO_HPA /* PCI bus */ @@ -36,5 +36,5 @@ #define PORT_SERIAL1 (DINO_UART_HPA + 0x800) #define PORT_SERIAL2 (LASI_UART_HPA + 0x800) -#define HPPA_MAX_CPUS 32 /* max. number of SMP CPUs */ +#define HPPA_MAX_CPUS 8 /* max. number of SMP CPUs */ #define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */ |