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| author | Mitsyanko Igor <i.mitsyanko@samsung.com> | 2012-02-16 09:56:06 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-02-17 11:13:14 +0000 |
| commit | 30628cb12de2e35d87cb04194113341b6a8922b2 (patch) | |
| tree | 013e37eb256c7d219af637d7e9b180dc8bdfb176 /hw/exynos4210.c | |
| parent | 2c2c6496f83b1746a118dbcb2a0e4f8c0305c2a8 (diff) | |
| download | qemu-30628cb12de2e35d87cb04194113341b6a8922b2.zip qemu-30628cb12de2e35d87cb04194113341b6a8922b2.tar.gz qemu-30628cb12de2e35d87cb04194113341b6a8922b2.tar.bz2 | |
Exynos4210: added display controller implementation
Exynos4210 display controller (FIMD) has 5 hardware windows with alpha and
chroma key blending functions.
Signed-off-by: Mitsyanko Igor <i.mitsyanko@samsung.com>
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/exynos4210.c')
| -rw-r--r-- | hw/exynos4210.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/hw/exynos4210.c b/hw/exynos4210.c index 558f669..f904370 100644 --- a/hw/exynos4210.c +++ b/hw/exynos4210.c @@ -58,6 +58,9 @@ /* PMU SFR base address */ #define EXYNOS4210_PMU_BASE_ADDR 0x10020000 +/* Display controllers (FIMD) */ +#define EXYNOS4210_FIMD0_BASE_ADDR 0x11C00000 + static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 0x09, 0x00, 0x00, 0x00 }; @@ -256,5 +259,12 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, EXYNOS4210_UART3_FIFO_SIZE, 3, NULL, s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); + /*** Display controller (FIMD) ***/ + sysbus_create_varargs("exynos4210.fimd", EXYNOS4210_FIMD0_BASE_ADDR, + s->irq_table[exynos4210_get_irq(11, 0)], + s->irq_table[exynos4210_get_irq(11, 1)], + s->irq_table[exynos4210_get_irq(11, 2)], + NULL); + return s; } |