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authorBALATON Zoltan <balaton@eik.bme.hu>2023-01-21 21:35:29 +0100
committerDaniel Henrique Barboza <danielhb413@gmail.com>2023-02-05 06:40:28 -0300
commitbd591dc1b3c39b7f73b8d9f20be6e9001c905238 (patch)
tree1f483395a149bd10cfed517fd31a1c7cf06a5a98 /hw/display
parent57ad5b5ae04ce39f406795e657ca1c03e98e29cf (diff)
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hw/display/sm501: Code style fix
Fix checkpatch warning about multi-line comment. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <8801292992a304609e1eac680fe36b515592b926.1674333199.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw/display')
-rw-r--r--hw/display/sm501.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/display/sm501.c b/hw/display/sm501.c
index 1e17072..e1d0591 100644
--- a/hw/display/sm501.c
+++ b/hw/display/sm501.c
@@ -1768,7 +1768,8 @@ static const GraphicHwOps sm501_ops = {
static void sm501_reset(SM501State *s)
{
s->system_control = 0x00100000; /* 2D engine FIFO empty */
- /* Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
+ /*
+ * Bits 17 (SH), 7 (CDR), 6:5 (Test), 2:0 (Bus) are all supposed
* to be determined at reset by GPIO lines which set config bits.
* We hardwire them:
* SH = 0 : Hitachi Ready Polarity == Active Low