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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-02-14 18:58:34 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-02-21 19:42:34 +0100 |
| commit | cefd68f6b1e20639ba95d4eb8b4a99b5e00d93d3 (patch) | |
| tree | f92a0b9f9d5edf88e7ffc9f0b121954db2f41534 /hw/display/vhost-user-gpu.c | |
| parent | 9f5f7691dee18b0a0d6e0d8e291b7c12da85de17 (diff) | |
| download | qemu-cefd68f6b1e20639ba95d4eb8b4a99b5e00d93d3.zip qemu-cefd68f6b1e20639ba95d4eb8b4a99b5e00d93d3.tar.gz qemu-cefd68f6b1e20639ba95d4eb8b4a99b5e00d93d3.tar.bz2 | |
target/mips: Promote 128-bit multimedia registers as global ones
The cpu::mmr[] array contains the upper halves of 128-bit GPR
registers. While they are only used by the R5900 CPU, the
concept is generic and could be used by another MIPS implementation.
Rename 'cpu::mmr' as 'cpu::gpr_hi' and make them global.
When the code is similar to the GPR lower halves, move it
close by.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-5-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'hw/display/vhost-user-gpu.c')
0 files changed, 0 insertions, 0 deletions