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| author | Yongbok Kim <yongbok.kim@imgtec.com> | 2015-06-30 15:44:28 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2015-07-15 14:07:17 +0100 |
| commit | d4f4f0d5d9e74c19614479592c8bc865d92773d0 (patch) | |
| tree | 5c11026b1c413633ef2c4ce567ba274089d322ec /hw/cpu | |
| parent | 4dc89b782095d7a0b919fafd7b1322b3cb1279f1 (diff) | |
| download | qemu-d4f4f0d5d9e74c19614479592c8bc865d92773d0.zip qemu-d4f4f0d5d9e74c19614479592c8bc865d92773d0.tar.gz qemu-d4f4f0d5d9e74c19614479592c8bc865d92773d0.tar.bz2 | |
target-mips: fix to clear MSACSR.Cause
MSACSR.Cause bits are needed to be cleared before a vector floating-point
instructions.
FEXDO.df, FEXUPL.df and FEXUPR.df were missed out.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'hw/cpu')
0 files changed, 0 insertions, 0 deletions