diff options
author | Paolo Bonzini <pbonzini@redhat.com> | 2013-02-05 16:36:44 +0100 |
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committer | Paolo Bonzini <pbonzini@redhat.com> | 2013-04-08 18:13:16 +0200 |
commit | 0434e30afb6175212389811e0b28b948eb3c1e40 (patch) | |
tree | 1e620f6e6078232b2d86322da51874df4e4d1960 /hw/cpu | |
parent | e28bee8ee654b81f4688a505e56ade0692174b5c (diff) | |
download | qemu-0434e30afb6175212389811e0b28b948eb3c1e40.zip qemu-0434e30afb6175212389811e0b28b948eb3c1e40.tar.gz qemu-0434e30afb6175212389811e0b28b948eb3c1e40.tar.bz2 |
hw: move ARM CPU cores to hw/cpu/, configure with default-configs/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/cpu')
-rw-r--r-- | hw/cpu/Makefile.objs | 4 | ||||
-rw-r--r-- | hw/cpu/a15mpcore.c | 114 | ||||
-rw-r--r-- | hw/cpu/a9mpcore.c | 138 | ||||
-rw-r--r-- | hw/cpu/arm11mpcore.c | 277 |
4 files changed, 533 insertions, 0 deletions
diff --git a/hw/cpu/Makefile.objs b/hw/cpu/Makefile.objs index e69de29..a49ca04 100644 --- a/hw/cpu/Makefile.objs +++ b/hw/cpu/Makefile.objs @@ -0,0 +1,4 @@ +obj-$(CONFIG_ARM11MPCORE) += arm11mpcore.o +obj-$(CONFIG_ARM9MPCORE) += a9mpcore.o +obj-$(CONFIG_ARM15MPCORE) += a15mpcore.o + diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c new file mode 100644 index 0000000..648656d --- /dev/null +++ b/hw/cpu/a15mpcore.c @@ -0,0 +1,114 @@ +/* + * Cortex-A15MPCore internal peripheral emulation. + * + * Copyright (c) 2012 Linaro Limited. + * Written by Peter Maydell. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "hw/sysbus.h" +#include "sysemu/kvm.h" + +/* A15MP private memory region. */ + +typedef struct A15MPPrivState { + SysBusDevice busdev; + uint32_t num_cpu; + uint32_t num_irq; + MemoryRegion container; + DeviceState *gic; +} A15MPPrivState; + +static void a15mp_priv_set_irq(void *opaque, int irq, int level) +{ + A15MPPrivState *s = (A15MPPrivState *)opaque; + qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); +} + +static int a15mp_priv_init(SysBusDevice *dev) +{ + A15MPPrivState *s = FROM_SYSBUS(A15MPPrivState, dev); + SysBusDevice *busdev; + const char *gictype = "arm_gic"; + + if (kvm_irqchip_in_kernel()) { + gictype = "kvm-arm-gic"; + } + + s->gic = qdev_create(NULL, gictype); + qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); + qdev_prop_set_uint32(s->gic, "revision", 2); + qdev_init_nofail(s->gic); + busdev = SYS_BUS_DEVICE(s->gic); + + /* Pass through outbound IRQ lines from the GIC */ + sysbus_pass_irq(dev, busdev); + + /* Pass through inbound GPIO lines to the GIC */ + qdev_init_gpio_in(&s->busdev.qdev, a15mp_priv_set_irq, s->num_irq - 32); + + /* Memory map (addresses are offsets from PERIPHBASE): + * 0x0000-0x0fff -- reserved + * 0x1000-0x1fff -- GIC Distributor + * 0x2000-0x2fff -- GIC CPU interface + * 0x4000-0x4fff -- GIC virtual interface control (not modelled) + * 0x5000-0x5fff -- GIC virtual interface control (not modelled) + * 0x6000-0x7fff -- GIC virtual CPU interface (not modelled) + */ + memory_region_init(&s->container, "a15mp-priv-container", 0x8000); + memory_region_add_subregion(&s->container, 0x1000, + sysbus_mmio_get_region(busdev, 0)); + memory_region_add_subregion(&s->container, 0x2000, + sysbus_mmio_get_region(busdev, 1)); + + sysbus_init_mmio(dev, &s->container); + return 0; +} + +static Property a15mp_priv_properties[] = { + DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1), + /* The Cortex-A15MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A15MP test chip in the + * Versatile Express A15 development board. + * Other boards may differ and should set this property appropriately. + */ + DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 96), + DEFINE_PROP_END_OF_LIST(), +}; + +static void a15mp_priv_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + k->init = a15mp_priv_init; + dc->props = a15mp_priv_properties; + /* We currently have no savable state */ +} + +static const TypeInfo a15mp_priv_info = { + .name = "a15mpcore_priv", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(A15MPPrivState), + .class_init = a15mp_priv_class_init, +}; + +static void a15mp_register_types(void) +{ + type_register_static(&a15mp_priv_info); +} + +type_init(a15mp_register_types) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c new file mode 100644 index 0000000..0a1a10f --- /dev/null +++ b/hw/cpu/a9mpcore.c @@ -0,0 +1,138 @@ +/* + * Cortex-A9MPCore internal peripheral emulation. + * + * Copyright (c) 2009 CodeSourcery. + * Copyright (c) 2011 Linaro Limited. + * Written by Paul Brook, Peter Maydell. + * + * This code is licensed under the GPL. + */ + +#include "hw/sysbus.h" + +typedef struct A9MPPrivState { + SysBusDevice busdev; + uint32_t num_cpu; + MemoryRegion container; + DeviceState *mptimer; + DeviceState *wdt; + DeviceState *gic; + DeviceState *scu; + uint32_t num_irq; +} A9MPPrivState; + +static void a9mp_priv_set_irq(void *opaque, int irq, int level) +{ + A9MPPrivState *s = (A9MPPrivState *)opaque; + qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); +} + +static int a9mp_priv_init(SysBusDevice *dev) +{ + A9MPPrivState *s = FROM_SYSBUS(A9MPPrivState, dev); + SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev; + int i; + + s->gic = qdev_create(NULL, "arm_gic"); + qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); + qdev_init_nofail(s->gic); + gicbusdev = SYS_BUS_DEVICE(s->gic); + + /* Pass through outbound IRQ lines from the GIC */ + sysbus_pass_irq(dev, gicbusdev); + + /* Pass through inbound GPIO lines to the GIC */ + qdev_init_gpio_in(&s->busdev.qdev, a9mp_priv_set_irq, s->num_irq - 32); + + s->scu = qdev_create(NULL, "a9-scu"); + qdev_prop_set_uint32(s->scu, "num-cpu", s->num_cpu); + qdev_init_nofail(s->scu); + scubusdev = SYS_BUS_DEVICE(s->scu); + + s->mptimer = qdev_create(NULL, "arm_mptimer"); + qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); + qdev_init_nofail(s->mptimer); + timerbusdev = SYS_BUS_DEVICE(s->mptimer); + + s->wdt = qdev_create(NULL, "arm_mptimer"); + qdev_prop_set_uint32(s->wdt, "num-cpu", s->num_cpu); + qdev_init_nofail(s->wdt); + wdtbusdev = SYS_BUS_DEVICE(s->wdt); + + /* Memory map (addresses are offsets from PERIPHBASE): + * 0x0000-0x00ff -- Snoop Control Unit + * 0x0100-0x01ff -- GIC CPU interface + * 0x0200-0x02ff -- Global Timer + * 0x0300-0x05ff -- nothing + * 0x0600-0x06ff -- private timers and watchdogs + * 0x0700-0x0fff -- nothing + * 0x1000-0x1fff -- GIC Distributor + * + * We should implement the global timer but don't currently do so. + */ + memory_region_init(&s->container, "a9mp-priv-container", 0x2000); + memory_region_add_subregion(&s->container, 0, + sysbus_mmio_get_region(scubusdev, 0)); + /* GIC CPU interface */ + memory_region_add_subregion(&s->container, 0x100, + sysbus_mmio_get_region(gicbusdev, 1)); + /* Note that the A9 exposes only the "timer/watchdog for this core" + * memory region, not the "timer/watchdog for core X" ones 11MPcore has. + */ + memory_region_add_subregion(&s->container, 0x600, + sysbus_mmio_get_region(timerbusdev, 0)); + memory_region_add_subregion(&s->container, 0x620, + sysbus_mmio_get_region(wdtbusdev, 0)); + memory_region_add_subregion(&s->container, 0x1000, + sysbus_mmio_get_region(gicbusdev, 0)); + + sysbus_init_mmio(dev, &s->container); + + /* Wire up the interrupt from each watchdog and timer. + * For each core the timer is PPI 29 and the watchdog PPI 30. + */ + for (i = 0; i < s->num_cpu; i++) { + int ppibase = (s->num_irq - 32) + i * 32; + sysbus_connect_irq(timerbusdev, i, + qdev_get_gpio_in(s->gic, ppibase + 29)); + sysbus_connect_irq(wdtbusdev, i, + qdev_get_gpio_in(s->gic, ppibase + 30)); + } + return 0; +} + +static Property a9mp_priv_properties[] = { + DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), + /* The Cortex-A9MP may have anything from 0 to 224 external interrupt + * IRQ lines (with another 32 internal). We default to 64+32, which + * is the number provided by the Cortex-A9MP test chip in the + * Realview PBX-A9 and Versatile Express A9 development boards. + * Other boards may differ and should set this property appropriately. + */ + DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), + DEFINE_PROP_END_OF_LIST(), +}; + +static void a9mp_priv_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = a9mp_priv_init; + dc->props = a9mp_priv_properties; +} + +static const TypeInfo a9mp_priv_info = { + .name = "a9mpcore_priv", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(A9MPPrivState), + .class_init = a9mp_priv_class_init, +}; + +static void a9mp_register_types(void) +{ + type_register_static(&a9mp_priv_info); +} + +type_init(a9mp_register_types) diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c new file mode 100644 index 0000000..90dcead --- /dev/null +++ b/hw/cpu/arm11mpcore.c @@ -0,0 +1,277 @@ +/* + * ARM11MPCore internal peripheral emulation. + * + * Copyright (c) 2006-2007 CodeSourcery. + * Written by Paul Brook + * + * This code is licensed under the GPL. + */ + +#include "hw/sysbus.h" +#include "qemu/timer.h" + +/* MPCore private memory region. */ + +typedef struct ARM11MPCorePriveState { + SysBusDevice busdev; + uint32_t scu_control; + int iomemtype; + uint32_t old_timer_status[8]; + uint32_t num_cpu; + MemoryRegion iomem; + MemoryRegion container; + DeviceState *mptimer; + DeviceState *wdtimer; + DeviceState *gic; + uint32_t num_irq; +} ARM11MPCorePriveState; + +/* Per-CPU private memory mapped IO. */ + +static uint64_t mpcore_scu_read(void *opaque, hwaddr offset, + unsigned size) +{ + ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; + int id; + /* SCU */ + switch (offset) { + case 0x00: /* Control. */ + return s->scu_control; + case 0x04: /* Configuration. */ + id = ((1 << s->num_cpu) - 1) << 4; + return id | (s->num_cpu - 1); + case 0x08: /* CPU status. */ + return 0; + case 0x0c: /* Invalidate all. */ + return 0; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "mpcore_priv_read: Bad offset %x\n", (int)offset); + return 0; + } +} + +static void mpcore_scu_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; + /* SCU */ + switch (offset) { + case 0: /* Control register. */ + s->scu_control = value & 1; + break; + case 0x0c: /* Invalidate all. */ + /* This is a no-op as cache is not emulated. */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "mpcore_priv_read: Bad offset %x\n", (int)offset); + } +} + +static const MemoryRegionOps mpcore_scu_ops = { + .read = mpcore_scu_read, + .write = mpcore_scu_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void mpcore_priv_set_irq(void *opaque, int irq, int level) +{ + ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; + qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); +} + +static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) +{ + int i; + SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic); + SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s->mptimer); + SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s->wdtimer); + memory_region_init(&s->container, "mpcode-priv-container", 0x2000); + memory_region_init_io(&s->iomem, &mpcore_scu_ops, s, "mpcore-scu", 0x100); + memory_region_add_subregion(&s->container, 0, &s->iomem); + /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs + * at 0x200, 0x300... + */ + for (i = 0; i < (s->num_cpu + 1); i++) { + hwaddr offset = 0x100 + (i * 0x100); + memory_region_add_subregion(&s->container, offset, + sysbus_mmio_get_region(gicbusdev, i + 1)); + } + /* Add the regions for timer and watchdog for "current CPU" and + * for each specific CPU. + */ + for (i = 0; i < (s->num_cpu + 1); i++) { + /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ + hwaddr offset = 0x600 + i * 0x100; + memory_region_add_subregion(&s->container, offset, + sysbus_mmio_get_region(timerbusdev, i)); + memory_region_add_subregion(&s->container, offset + 0x20, + sysbus_mmio_get_region(wdtbusdev, i)); + } + memory_region_add_subregion(&s->container, 0x1000, + sysbus_mmio_get_region(gicbusdev, 0)); + /* Wire up the interrupt from each watchdog and timer. + * For each core the timer is PPI 29 and the watchdog PPI 30. + */ + for (i = 0; i < s->num_cpu; i++) { + int ppibase = (s->num_irq - 32) + i * 32; + sysbus_connect_irq(timerbusdev, i, + qdev_get_gpio_in(s->gic, ppibase + 29)); + sysbus_connect_irq(wdtbusdev, i, + qdev_get_gpio_in(s->gic, ppibase + 30)); + } +} + +static int mpcore_priv_init(SysBusDevice *dev) +{ + ARM11MPCorePriveState *s = FROM_SYSBUS(ARM11MPCorePriveState, dev); + + s->gic = qdev_create(NULL, "arm_gic"); + qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); + /* Request the legacy 11MPCore GIC behaviour: */ + qdev_prop_set_uint32(s->gic, "revision", 0); + qdev_init_nofail(s->gic); + + /* Pass through outbound IRQ lines from the GIC */ + sysbus_pass_irq(dev, SYS_BUS_DEVICE(s->gic)); + + /* Pass through inbound GPIO lines to the GIC */ + qdev_init_gpio_in(&s->busdev.qdev, mpcore_priv_set_irq, s->num_irq - 32); + + s->mptimer = qdev_create(NULL, "arm_mptimer"); + qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); + qdev_init_nofail(s->mptimer); + + s->wdtimer = qdev_create(NULL, "arm_mptimer"); + qdev_prop_set_uint32(s->wdtimer, "num-cpu", s->num_cpu); + qdev_init_nofail(s->wdtimer); + + mpcore_priv_map_setup(s); + sysbus_init_mmio(dev, &s->container); + return 0; +} + +/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ + controllers. The output of these, plus some of the raw input lines + are fed into a single SMP-aware interrupt controller on the CPU. */ +typedef struct { + SysBusDevice busdev; + SysBusDevice *priv; + qemu_irq cpuic[32]; + qemu_irq rvic[4][64]; + uint32_t num_cpu; +} mpcore_rirq_state; + +/* Map baseboard IRQs onto CPU IRQ lines. */ +static const int mpcore_irq_map[32] = { + -1, -1, -1, -1, 1, 2, -1, -1, + -1, -1, 6, -1, 4, 5, -1, -1, + -1, 14, 15, 0, 7, 8, -1, -1, + -1, -1, -1, -1, 9, 3, -1, -1, +}; + +static void mpcore_rirq_set_irq(void *opaque, int irq, int level) +{ + mpcore_rirq_state *s = (mpcore_rirq_state *)opaque; + int i; + + for (i = 0; i < 4; i++) { + qemu_set_irq(s->rvic[i][irq], level); + } + if (irq < 32) { + irq = mpcore_irq_map[irq]; + if (irq >= 0) { + qemu_set_irq(s->cpuic[irq], level); + } + } +} + +static int realview_mpcore_init(SysBusDevice *dev) +{ + mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev); + DeviceState *gic; + DeviceState *priv; + int n; + int i; + + priv = qdev_create(NULL, "arm11mpcore_priv"); + qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); + qdev_init_nofail(priv); + s->priv = SYS_BUS_DEVICE(priv); + sysbus_pass_irq(dev, s->priv); + for (i = 0; i < 32; i++) { + s->cpuic[i] = qdev_get_gpio_in(priv, i); + } + /* ??? IRQ routing is hardcoded to "normal" mode. */ + for (n = 0; n < 4; n++) { + gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000, + s->cpuic[10 + n]); + for (i = 0; i < 64; i++) { + s->rvic[n][i] = qdev_get_gpio_in(gic, i); + } + } + qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64); + sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0)); + return 0; +} + +static Property mpcore_rirq_properties[] = { + DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mpcore_rirq_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = realview_mpcore_init; + dc->props = mpcore_rirq_properties; +} + +static const TypeInfo mpcore_rirq_info = { + .name = "realview_mpcore", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(mpcore_rirq_state), + .class_init = mpcore_rirq_class_init, +}; + +static Property mpcore_priv_properties[] = { + DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), + /* The ARM11 MPCORE TRM says the on-chip controller may have + * anything from 0 to 224 external interrupt IRQ lines (with another + * 32 internal). We default to 32+32, which is the number provided by + * the ARM11 MPCore test chip in the Realview Versatile Express + * coretile. Other boards may differ and should set this property + * appropriately. Some Linux kernels may not boot if the hardware + * has more IRQ lines than the kernel expects. + */ + DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mpcore_priv_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = mpcore_priv_init; + dc->props = mpcore_priv_properties; +} + +static const TypeInfo mpcore_priv_info = { + .name = "arm11mpcore_priv", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(ARM11MPCorePriveState), + .class_init = mpcore_priv_class_init, +}; + +static void arm11mpcore_register_types(void) +{ + type_register_static(&mpcore_rirq_info); + type_register_static(&mpcore_priv_info); +} + +type_init(arm11mpcore_register_types) |