aboutsummaryrefslogtreecommitdiff
path: root/hw/cpu
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2015-08-13 11:26:22 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-08-13 11:26:22 +0100
commit5dfaa75b4d96fe88858a98d947b97e697e2811e6 (patch)
treec692940bbc163d16adc25679bb692a5ee7714075 /hw/cpu
parenta007b1f85813ef6450ad3e761e46c189e3f40e04 (diff)
downloadqemu-5dfaa75b4d96fe88858a98d947b97e697e2811e6.zip
qemu-5dfaa75b4d96fe88858a98d947b97e697e2811e6.tar.gz
qemu-5dfaa75b4d96fe88858a98d947b97e697e2811e6.tar.bz2
hw/cpu/a15mpcore: Wire up hyp and secure physical timer interrupts
Since we now support both the hypervisor and the secure physical timer, wire their interrupt lines up in the a15mpcore wrapper object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1437047249-2357-5-git-send-email-peter.maydell@linaro.org Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'hw/cpu')
-rw-r--r--hw/cpu/a15mpcore.c21
1 files changed, 14 insertions, 7 deletions
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index e31a1f9..58ac02e 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -75,14 +75,21 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
for (i = 0; i < s->num_cpu; i++) {
DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
int ppibase = s->num_irq - 32 + i * 32;
- /* physical timer; we wire it up to the non-secure timer's ID,
- * since a real A15 always has TrustZone but QEMU doesn't.
+ int irq;
+ /* Mapping from the output timer irq lines from the CPU to the
+ * GIC PPI inputs used on the A15:
*/
- qdev_connect_gpio_out(cpudev, 0,
- qdev_get_gpio_in(gicdev, ppibase + 30));
- /* virtual timer */
- qdev_connect_gpio_out(cpudev, 1,
- qdev_get_gpio_in(gicdev, ppibase + 27));
+ const int timer_irq[] = {
+ [GTIMER_PHYS] = 30,
+ [GTIMER_VIRT] = 27,
+ [GTIMER_HYP] = 26,
+ [GTIMER_SEC] = 29,
+ };
+ for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
+ qdev_connect_gpio_out(cpudev, irq,
+ qdev_get_gpio_in(gicdev,
+ ppibase + timer_irq[irq]));
+ }
}
/* Memory map (addresses are offsets from PERIPHBASE):