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author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2014-01-06 10:16:38 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2014-01-08 19:07:21 +0000 |
commit | 676f4c095d53841626b1ee2cbc7a53b4f6239e4e (patch) | |
tree | a91feceb712e44948d43e1bbc9b51c04de834902 /hw/char | |
parent | 1e77c91e2422ffa366fa5a0a39a6e7cc24a102ca (diff) | |
download | qemu-676f4c095d53841626b1ee2cbc7a53b4f6239e4e.zip qemu-676f4c095d53841626b1ee2cbc7a53b4f6239e4e.tar.gz qemu-676f4c095d53841626b1ee2cbc7a53b4f6239e4e.tar.bz2 |
char/cadence_uart: Simplify status generation
The status register bits are always pure functions of other device
state. Move the generation of these bits to the update_status()
function to simplify. Makes developing much easier as theres now no need
to recheck status bits on all the changes to rx/tx fifo state.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 321994929f789096975104f99c55732774be4cae.1388626249.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/char')
-rw-r--r-- | hw/char/cadence_uart.c | 33 |
1 files changed, 8 insertions, 25 deletions
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index d6abc5b..ddd7267 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -128,6 +128,13 @@ typedef struct { static void uart_update_status(UartState *s) { + s->r[R_SR] = 0; + + s->r[R_SR] |= s->rx_count == RX_FIFO_SIZE ? UART_SR_INTR_RFUL : 0; + s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0; + s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0; + + s->r[R_SR] |= UART_SR_INTR_TEMPTY; s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK; qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR])); } @@ -166,15 +173,10 @@ static void uart_rx_reset(UartState *s) if (s->chr) { qemu_chr_accept_input(s->chr); } - - s->r[R_SR] |= UART_SR_INTR_REMPTY; - s->r[R_SR] &= ~UART_SR_INTR_RFUL; } static void uart_tx_reset(UartState *s) { - s->r[R_SR] |= UART_SR_INTR_TEMPTY; - s->r[R_SR] &= ~UART_SR_INTR_TFUL; } static void uart_send_breaks(UartState *s) @@ -274,8 +276,6 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) return; } - s->r[R_SR] &= ~UART_SR_INTR_REMPTY; - if (s->rx_count == RX_FIFO_SIZE) { s->r[R_CISR] |= UART_INTR_ROVR; } else { @@ -283,15 +283,6 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size) s->rx_fifo[s->rx_wpos] = buf[i]; s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE; s->rx_count++; - - if (s->rx_count == RX_FIFO_SIZE) { - s->r[R_SR] |= UART_SR_INTR_RFUL; - break; - } - - if (s->rx_count >= s->r[R_RTRIG]) { - s->r[R_SR] |= UART_SR_INTR_RTRIG; - } } timer_mod(s->fifo_trigger_handle, new_rx_time + (s->char_tx_time * 4)); @@ -339,26 +330,17 @@ static void uart_read_rx_fifo(UartState *s, uint32_t *c) return; } - s->r[R_SR] &= ~UART_SR_INTR_RFUL; - if (s->rx_count) { uint32_t rx_rpos = (RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE; *c = s->rx_fifo[rx_rpos]; s->rx_count--; - if (!s->rx_count) { - s->r[R_SR] |= UART_SR_INTR_REMPTY; - } qemu_chr_accept_input(s->chr); } else { *c = 0; - s->r[R_SR] |= UART_SR_INTR_REMPTY; } - if (s->rx_count < s->r[R_RTRIG]) { - s->r[R_SR] &= ~UART_SR_INTR_RTRIG; - } uart_update_status(s); } @@ -447,6 +429,7 @@ static void cadence_uart_reset(DeviceState *dev) s->rx_count = 0; s->rx_wpos = 0; + uart_update_status(s); } static int cadence_uart_init(SysBusDevice *dev) |