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| author | BALATON Zoltan <balaton@eik.bme.hu> | 2021-10-29 23:02:09 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-10-30 18:39:37 +0200 |
| commit | 2f6df13748a7de19ab150a52af846f70303746e5 (patch) | |
| tree | f605aef58b8f153e7d62b3ecbd01b6825b25276f /hw/char | |
| parent | 3cf7ce4337aebf8f9148ee53033710b4c4b00f01 (diff) | |
| download | qemu-2f6df13748a7de19ab150a52af846f70303746e5.zip qemu-2f6df13748a7de19ab150a52af846f70303746e5.tar.gz qemu-2f6df13748a7de19ab150a52af846f70303746e5.tar.bz2 | |
hw/char/sh_serial: Rename type sh_serial_state to SHSerialState
Coding style says types should be camel case.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <0f185653528c99eeeb2b4e4afb8b818d93298c20.1635541329.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'hw/char')
| -rw-r--r-- | hw/char/sh_serial.c | 24 |
1 files changed, 11 insertions, 13 deletions
diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 2d6ea00..bc5e0c4 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -73,9 +73,9 @@ typedef struct { qemu_irq txi; qemu_irq tei; qemu_irq bri; -} sh_serial_state; +} SHSerialState; -static void sh_serial_clear_fifo(sh_serial_state *s) +static void sh_serial_clear_fifo(SHSerialState *s) { memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH); s->rx_cnt = 0; @@ -86,7 +86,7 @@ static void sh_serial_clear_fifo(sh_serial_state *s) static void sh_serial_write(void *opaque, hwaddr offs, uint64_t val, unsigned size) { - sh_serial_state *s = opaque; + SHSerialState *s = opaque; unsigned char ch; trace_sh_serial_write(size, offs, val); @@ -204,7 +204,7 @@ static void sh_serial_write(void *opaque, hwaddr offs, static uint64_t sh_serial_read(void *opaque, hwaddr offs, unsigned size) { - sh_serial_state *s = opaque; + SHSerialState *s = opaque; uint32_t ret = UINT32_MAX; #if 0 @@ -309,12 +309,12 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs, return ret; } -static int sh_serial_can_receive(sh_serial_state *s) +static int sh_serial_can_receive(SHSerialState *s) { return s->scr & (1 << 4); } -static void sh_serial_receive_break(sh_serial_state *s) +static void sh_serial_receive_break(SHSerialState *s) { if (s->feat & SH_SERIAL_FEAT_SCIF) { s->sr |= (1 << 4); @@ -323,13 +323,13 @@ static void sh_serial_receive_break(sh_serial_state *s) static int sh_serial_can_receive1(void *opaque) { - sh_serial_state *s = opaque; + SHSerialState *s = opaque; return sh_serial_can_receive(s); } static void sh_serial_timeout_int(void *opaque) { - sh_serial_state *s = opaque; + SHSerialState *s = opaque; s->flags |= SH_SERIAL_FLAG_RDF; if (s->scr & (1 << 6) && s->rxi) { @@ -339,7 +339,7 @@ static void sh_serial_timeout_int(void *opaque) static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) { - sh_serial_state *s = opaque; + SHSerialState *s = opaque; if (s->feat & SH_SERIAL_FEAT_SCIF) { int i; @@ -369,7 +369,7 @@ static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size) static void sh_serial_event(void *opaque, QEMUChrEvent event) { - sh_serial_state *s = opaque; + SHSerialState *s = opaque; if (event == CHR_EVENT_BREAK) { sh_serial_receive_break(s); } @@ -390,9 +390,7 @@ void sh_serial_init(MemoryRegion *sysmem, qemu_irq tei_source, qemu_irq bri_source) { - sh_serial_state *s; - - s = g_malloc0(sizeof(sh_serial_state)); + SHSerialState *s = g_malloc0(sizeof(*s)); s->feat = feat; s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE; |