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| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2021-09-03 12:32:18 +0100 |
|---|---|---|
| committer | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2021-09-08 11:09:45 +0100 |
| commit | bf4fbb69f36d9697a7d62d767de024fd9062d31d (patch) | |
| tree | 7e4e6f3824736601216ae906c2add0da9314aa9a /hw/char/trace-events | |
| parent | 8e8aa96590156577ed8a2623d1a2e4db4e5748b8 (diff) | |
| download | qemu-bf4fbb69f36d9697a7d62d767de024fd9062d31d.zip qemu-bf4fbb69f36d9697a7d62d767de024fd9062d31d.tar.gz qemu-bf4fbb69f36d9697a7d62d767de024fd9062d31d.tar.bz2 | |
escc: introduce escc_hard_reset_chn() for hardware reset
This new hardware reset function is to be called for both channels when the
hardware reset bit is written to register WR9. Its initial implementation is
the same as the existing escc_reset_chn() function used for device reset.
Add a new trace event when the guest initiates a hard reset via the WR9 register
to help diagnose guest reset issues.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210903113223.19551-5-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'hw/char/trace-events')
| -rw-r--r-- | hw/char/trace-events | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/char/trace-events b/hw/char/trace-events index 073f98e..b774832 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -36,6 +36,7 @@ grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" va grlib_apbuart_readl_unknown(uint64_t addr) "addr 0x%"PRIx64 # escc.c +escc_hard_reset(void) "hard reset" escc_soft_reset_chn(char channel) "soft reset channel %c" escc_put_queue(char channel, int b) "channel %c put: 0x%02x" escc_get_queue(char channel, int val) "channel %c get 0x%02x" |