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| author | Axel Heider <axel.heider@hensoldt.net> | 2022-10-25 20:32:30 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-01-05 12:14:43 +0000 |
| commit | 2ca267fd36a275c771528bd5ae50ae8406155ad9 (patch) | |
| tree | 8dcbbe806fb97a5657f94767414ddc0396196d3a /hw/char/escc.c | |
| parent | 1ead962edf1297e223a039167429d4c986bfb90e (diff) | |
| download | qemu-2ca267fd36a275c771528bd5ae50ae8406155ad9.zip qemu-2ca267fd36a275c771528bd5ae50ae8406155ad9.tar.gz qemu-2ca267fd36a275c771528bd5ae50ae8406155ad9.tar.bz2 | |
hw/timer/imx_epit: update interrupt state on CR write access
The interrupt state can change due to:
- reset clears both SR.OCIF and CR.OCIE
- write to CR.EN or CR.OCIE
Signed-off-by: Axel Heider <axel.heider@hensoldt.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/char/escc.c')
0 files changed, 0 insertions, 0 deletions