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| author | Peter Maydell <peter.maydell@linaro.org> | 2012-05-02 16:49:39 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-06-19 13:24:44 +0000 |
| commit | c48c6522f550b9b704f7324164b00b5770ec7345 (patch) | |
| tree | a5f501720f44e20f94ee985ce9c46b0154ed9445 /hw/arm_gic.c | |
| parent | acd684280f9e91e8199d0b2126d4b057676dafec (diff) | |
| download | qemu-c48c6522f550b9b704f7324164b00b5770ec7345.zip qemu-c48c6522f550b9b704f7324164b00b5770ec7345.tar.gz qemu-c48c6522f550b9b704f7324164b00b5770ec7345.tar.bz2 | |
hw/arm_gic: Remove the special casing of NCPU for the NVIC
Drop the special casing of NCPU=1 for the NVIC. This slightly
increases the amount of memory used by its state structure,
but removes some ifdeffery and means we can safely move the
GIC state into a common subclass structure.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm_gic.c')
| -rw-r--r-- | hw/arm_gic.c | 23 |
1 files changed, 3 insertions, 20 deletions
diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 17b2eba..2d8ceb8 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -25,11 +25,7 @@ /* First 32 are private to each CPU (SGIs and PPIs). */ #define GIC_INTERNAL 32 /* Maximum number of possible CPU interfaces, determined by GIC architecture */ -#ifdef NVIC -#define NCPU 1 -#else #define NCPU 8 -#endif //#define DEBUG_GIC @@ -67,11 +63,7 @@ typedef struct gic_irq_state } gic_irq_state; #define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1))) -#if NCPU > 1 #define NUM_CPU(s) ((s)->num_cpu) -#else -#define NUM_CPU(s) 1 -#endif #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm) #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm) @@ -131,11 +123,9 @@ typedef struct gic_state static inline int gic_get_current_cpu(gic_state *s) { -#if NCPU > 1 if (s->num_cpu > 1) { return cpu_single_env->cpu_index; } -#endif return 0; } @@ -842,21 +832,14 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id) return 0; } -#if NCPU > 1 -static void gic_init(gic_state *s, int num_cpu, int num_irq) -#else static void gic_init(gic_state *s, int num_irq) -#endif { int i; -#if NCPU > 1 - s->num_cpu = num_cpu; if (s->num_cpu > NCPU) { hw_error("requested %u CPUs exceeds GIC maximum %d\n", - num_cpu, NCPU); + s->num_cpu, NCPU); } -#endif s->num_irq = num_irq + GIC_BASE_IRQ; if (s->num_irq > GIC_MAXIRQ) { hw_error("requested %u interrupt lines exceeds GIC maximum %d\n", @@ -880,7 +863,7 @@ static void gic_init(gic_state *s, int num_irq) * [N+32..N+63] PPIs for CPU 1 * ... */ - i += (GIC_INTERNAL * num_cpu); + i += (GIC_INTERNAL * s->num_cpu); #endif qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i); for (i = 0; i < NUM_CPU(s); i++) { @@ -915,7 +898,7 @@ static int arm_gic_init(SysBusDevice *dev) /* Device instance init function for the GIC sysbus device */ int i; gic_state *s = FROM_SYSBUS(gic_state, dev); - gic_init(s, s->num_cpu, s->num_irq); + gic_init(s, s->num_irq); /* Distributor */ sysbus_init_mmio(dev, &s->iomem); /* cpu interfaces (one for "current cpu" plus one per cpu) */ |