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| author | Cédric Le Goater <clg@kaod.org> | 2019-07-01 17:26:17 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-07-01 17:28:59 +0100 |
| commit | 6da4433fc5fa8aff1096cc651c8d313c70ee6f4d (patch) | |
| tree | 0ffaad3157d8abb9216a61ca5996a5d95ac38bd7 /hw/arm | |
| parent | ad1a9782186d0ed1c02eb008f268d34599a54a42 (diff) | |
| download | qemu-6da4433fc5fa8aff1096cc651c8d313c70ee6f4d.zip qemu-6da4433fc5fa8aff1096cc651c8d313c70ee6f4d.tar.gz qemu-6da4433fc5fa8aff1096cc651c8d313c70ee6f4d.tar.bz2 | |
aspeed/smc: add a 'sdram_base' property
The DRAM address of a DMA transaction depends on the DRAM base address
of the SoC. Inform the SMC controller model with this value.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190618165311.27066-15-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm')
| -rw-r--r-- | hw/arm/aspeed_soc.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 736e523..02feb43 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -337,6 +337,12 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) aspeed_soc_get_irq(s, ASPEED_I2C)); /* FMC, The number of CS is set at the board level */ + object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM], + "sdram-base", &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err); if (err) { error_propagate(errp, err); |