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| author | Cédric Le Goater <clg@kaod.org> | 2016-10-17 19:22:17 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-10-17 19:22:17 +0100 |
| commit | a03cb1daf1a4e6ccce8632e13373eef8c4f9cba4 (patch) | |
| tree | 6dabeaa8c2d072321f1a8378b3fabb2ba2158333 /hw/arm | |
| parent | 2da95fd88b87bd90e39caeaf94943023b85dbe93 (diff) | |
| download | qemu-a03cb1daf1a4e6ccce8632e13373eef8c4f9cba4.zip qemu-a03cb1daf1a4e6ccce8632e13373eef8c4f9cba4.tar.gz qemu-a03cb1daf1a4e6ccce8632e13373eef8c4f9cba4.tar.bz2 | |
aspeed: add support for the SMC segment registers
The SMC controller on the Aspeed SoC has a set of registers to
configure the mapping of each flash module in the SoC address
space. Writing to these registers triggers a remap of the memory
region and the spec requires a certain number of checks before doing
so.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1474977462-28032-7-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm')
0 files changed, 0 insertions, 0 deletions